Datasheet > MTC16C2085S1UC48B

MTC16C2085S1UC48B

更新时间： 2024-04-09 19:02:53

品牌	Logo	应用领域
镁光 - MICRON		/
页数	文件大小	规格书
8页	306K
描述
MTC16C2085S1UC – 32GB

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32GB (x64, DR) 288-Pin DDR5 UDIMM

Features

DDR5 SDRAM UDIMM Addendum

MTC16C2085S1UC – 32GB

16Gb Die Revision A

Figure 1: 288-Pin DDR5 UDIMM (R/C-A0)

Features

Information provided here is in addition to or super-

sedes information provided in the Micron DDR5

UDIMM Core data sheet.

U10

• DDR5 functionality and operations supported as

defined in the component data sheet

Primary side

• Features and specifications defined in the Micron

DDR5 UDIMM core data sheet

• 288-pin, DDR5 unbuffered dual in-line memory

U11

U12

U13

U14

U15

U16

U17

U18

module (DDR5 UDIMM)

• Fast data transfer rate: PC5-4800, PC5-5600

• 32GB (4 Gig x 64)

Secondary side

Options

Marking

• Dual-rank

• Operating temperature

– Commercial (0°C ≤ T_OPER≤ 95°C)

• Frequency/CAS latency

• 32 internal banks; 8 groups of 4 banks each

48B

56B

– 0.416ns @ CL = 40 (DDR5-4800)

– 0.357ns @ CL = 46 (DDR5-5600)

Table 1: Addressing

Parameter

32GB

Row address ¹

64K (R0-R15)

Column address ¹

1K (C0-C9)

8 (BG0-BG2)

4 (BA0-BA1)

Device bank group address ¹

Device bank address per bank group ¹

Device configuration

16Gb (2Gb x 8), 32 banks

2 (CS0_n, CS1_n)

Module rank address

Notes: 1. These parameters represent the logical address state of the CA bus for different commands. Refer to the command

truth table in the component data sheet.

CCM005-802248454-15

mtc16c2085s1uc_drx8_udimm_dierevA.pdf - Rev. F 10/2021

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

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