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MTB52N06VL

更新时间： 2024-11-18 22:45:51
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 晶体晶体管功率场效应晶体管开关脉冲局域网
页数 文件大小 规格书
10页 204K
描述
TMOS POWER FET 52 AMPERES 60 VOLTS

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中文翻译

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MTB52N06VL 技术参数

生命周期：Transferred包装说明：SMALL OUTLINE, R-PSSO-G2
Reach Compliance Code：unknown风险等级：5.14
Is Samacsys：N其他特性：AVALANCHE RATED, LOGIC LEVEL COMPATIBLE
雪崩能效等级（Eas）：406 mJ外壳连接：DRAIN
配置：SINGLE WITH BUILT-IN DIODE最小漏源击穿电压：60 V
最大漏极电流 (Abs) (ID)：52 A最大漏极电流 (ID)：52 A
最大漏源导通电阻：0.025 ΩFET 技术：METAL-OXIDE SEMICONDUCTOR
最大反馈电容 (Crss)：340 pFJESD-30 代码：R-PSSO-G2
JESD-609代码：e0元件数量：1
端子数量：2工作模式：ENHANCEMENT MODE
最高工作温度：175 °C封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
极性/信道类型：N-CHANNEL功耗环境最大值：165 W
最大功率耗散 (Abs)：165 W最大脉冲漏极电流 (IDM)：182 A
认证状态：Not Qualified子类别：FET General Purpose Power
表面贴装：YES端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子位置：SINGLE
晶体管应用：SWITCHING晶体管元件材料：SILICON
最大关闭时间（toff）：520 ns最大开启时间（吨）：780 ns
Base Number Matches：1

MTB52N06VL 数据手册

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Order this document  
by MTB52N06VL/D  
SEMICONDUCTOR TECHNICAL DATA  
Motorola Preferred Device  
TMOS POWER FET  
52 AMPERES  
60 VOLTS  
N–Channel Enhancement–Mode Silicon Gate  
TMOS V is a new technology designed to achieve an on–resistance  
area product about one–half that of standard MOSFETs. This new  
technology more than doubles the present cell density of our 50  
and 60 volt TMOS devices. Just as with our TMOS E–FET designs,  
TMOS V is designed to withstand high energy in the avalanche and  
commutation modes. Designed for low voltage, high speed  
switching applications in power supplies, converters and power  
motor controls, these devices are particularly well suited for bridge  
circuits where diode speed and commutating safe operating areas  
are critical and offer additional safety margin against unexpected  
voltage transients.  
R
= 0.025 OHM  
DS(on)  
TM  
D
New Features of TMOS V  
G
•
On–resistance Area Product about One–half that of Standard  
MOSFETs with New Low Voltage, Low R Technology  
DS(on)  
Faster Switching than E–FET Predecessors  
CASE 418B–02, Style 2  
•
S
2
D PAK  
Features Common to TMOS V and TMOS E–FETs  
•
•
•
•
Avalanche Energy Specified  
and V Specified at Elevated Temperature  
Static Parameters are the Same for both TMOS V and TMOS E–FET  
Surface Mount Package Available in 16 mm 13–inch/2500 Unit  
Tape & Reel, Add T4 Suffix to Part Number  
I
DSS  
DS(on)  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
C
Rating  
Symbol  
Value  
60  
Unit  
Vdc  
Vdc  
Drain–to–Source Voltage  
V
DSS  
Drain–to–Gate Voltage (R  
GS  
= 1.0 MΩ)  
V
DGR  
60  
Gate–to–Source Voltage — Continuous  
— Non–Repetitive (t ≤ 10 ms)  
V
±15  
±25  
Vdc  
Vpk  
GS  
V
GSM  
p
Drain Current — Continuous  
— Continuous @ 100°C  
— Single Pulse (t ≤ 10 µs)  
I
I
52  
41  
182  
Adc  
D
D
I
Apk  
p
DM  
Total Power Dissipation  
Derate above 25°C  
Total Power Dissipation @ T = 25°C (1)  
P
D
188  
1.25  
3.0  
Watts  
W/°C  
Watts  
A
Operating and Storage Temperature Range  
T , T  
stg  
– 55 to 175  
406  
°C  
J
Single Pulse Drain–to–Source Avalanche Energy — STARTING T = 25°C  
E
AS  
mJ  
J
(V  
DD  
= 25 Vdc, V  
= 5 Vdc, PEAK I = 52 Apk, L = 0.3 mH, R = 25 Ω)  
GS L G  
Thermal Resistance — Junction to Case  
— Junction to Ambient  
R
θJC  
R
θJA  
R
θJA  
0.8  
62.5  
50  
°C/W  
— Junction to Ambient (1)  
Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 seconds  
T
L
260  
°C  
(1) When surface mounted to an FR4 board using the minimum recommended pad size.  
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit  
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.  
E–FET, Designer’s, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.  
Thermal Clad is a trademark of the Bergquist Company.  
Preferred devices are Motorola recommended choices for future use and best overall value.  
REV 3  
Motorola, Inc. 1996  
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