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MTB4N80E PDF预览

MTB4N80E

更新时间： 2024-11-05 21:22:31
品牌 Logo 应用领域
安森美 - ONSEMI 晶体管
页数 文件大小 规格书
10页 238K
描述
4A, 800V, 3ohm, N-CHANNEL, Si, POWER, MOSFET, D2PAK-3

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中文翻译

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MTB4N80E 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：D2PAK-3针数：3
Reach Compliance Code：not_compliantECCN代码：EAR99
风险等级：5.27Is Samacsys：N
雪崩能效等级（Eas）：320 mJ外壳连接：DRAIN
配置：SINGLE WITH BUILT-IN DIODE最小漏源击穿电压：800 V
最大漏极电流 (Abs) (ID)：4 A最大漏极电流 (ID)：4 A
最大漏源导通电阻：3 ΩFET 技术：METAL-OXIDE SEMICONDUCTOR
JESD-30 代码：R-PSSO-G2JESD-609代码：e0
元件数量：1端子数量：2
工作模式：ENHANCEMENT MODE最高工作温度：150 °C
封装主体材料：PLASTIC/EPOXY封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
极性/信道类型：N-CHANNEL最大功率耗散 (Abs)：125 W
最大脉冲漏极电流 (IDM)：12 A认证状态：Not Qualified
子类别：FET General Purpose Power表面贴装：YES
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子位置：SINGLE处于峰值回流温度下的最长时间：NOT SPECIFIED
晶体管应用：SWITCHING晶体管元件材料：SILICON
Base Number Matches：1

MTB4N80E 数据手册

 浏览型号MTB4N80E的Datasheet PDF文件第2页浏览型号MTB4N80E的Datasheet PDF文件第3页浏览型号MTB4N80E的Datasheet PDF文件第4页浏览型号MTB4N80E的Datasheet PDF文件第5页浏览型号MTB4N80E的Datasheet PDF文件第6页浏览型号MTB4N80E的Datasheet PDF文件第7页 
Order this document  
by MTB4N80E/D  
SEMICONDUCTOR TECHNICAL DATA  
Motorola Preferred Device  
TMOS POWER FET  
4.0 AMPERES  
800 VOLTS  
N–Channel Enhancement–Mode Silicon Gate  
2
The D PAK package has the capability of housing a larger die  
R
= 3.0 OHM  
DS(on)  
than any existing surface mount package which allows it to be used  
in applications that require the use of surface mount components  
with higher power and lower R  
capabilities. This high voltage  
DS(on)  
MOSFET uses an advanced termination scheme to provide  
enhanced voltage–blocking capability without degrading perfor-  
mance over time. In addition, this advanced TMOS E–FET is  
designed to withstand high energy in the avalanche and commuta-  
tion modes. The new energy efficient design also offers a  
drain–to–source diode with a fast recovery time. Designed for high  
voltage, high speed switching applications in power supplies,  
converters and PWM motor controls, these devices are particularly  
well suited for bridge circuits where diode speed and commutating  
safe operating areas are critical and offer additional safety margin  
against unexpected voltage transients.  
D
G
CASE 418B–02, Style 2  
2
D PAK  
•
•
•
Robust High Voltage Termination  
Avalanche Energy Specified  
Source–to–Drain Diode Recovery Time Comparable to a  
Discrete Fast Recovery Diode  
S
•
•
•
•
•
Diode is Characterized for Use in Bridge Circuits  
I
and V  
Specified at Elevated Temperature  
DSS  
DS(on)  
Short Heatsink Tab Manufactured — Not Sheared  
Specially Designed Leadframe for Maximum Power Dissipation  
Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
C
Rating  
Symbol  
Value  
800  
Unit  
Vdc  
Vdc  
Drain–Source Voltage  
V
DSS  
Drain–Gate Voltage (R  
= 1.0 MΩ)  
Gate–Source Voltage — Continuous  
V
DGR  
800  
GS  
V
± 20  
± 40  
Vdc  
Vpk  
GS  
Gate–Source Voltage — Non–Repetitive (t ≤ 10 ms)  
V
GSM  
p
Drain Current — Continuous  
Drain Current — Continuous @ 100°C  
Drain Current — Single Pulse (t ≤ 10 µs)  
I
I
4.0  
2.9  
12  
Adc  
D
D
I
Apk  
p
DM  
Total Power Dissipation  
Derate above 25°C  
P
D
125  
1.0  
2.5  
Watts  
W/°C  
Watts  
Total Power Dissipation @ T = 25°C, when mounted with the minimum recommended pad size  
A
Operating and Storage Temperature Range  
T , T  
stg  
– 55 to 150  
320  
°C  
J
Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C  
E
AS  
mJ  
J
(V  
DD  
= 100 Vdc, V  
= 10 Vdc, I = 8.0 Apk, L = 10 mH, R = 25 Ω)  
GS L G  
Thermal Resistance — Junction to Case  
Thermal Resistance — Junction to Ambient  
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size  
R
θJC  
R
θJA  
R
θJA  
1.0  
62.5  
50  
°C/W  
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds  
T
L
260  
°C  
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit  
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.  
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.  
Thermal Clad is a trademark of the Bergquist Company.  
Preferred devices are Motorola recommended choices for future use and best overall value.  
REV 4  
Motorola, Inc. 1996  
1234567...10

中文翻译

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MTB4N80E 替代型号

型号 品牌 替代类型 描述 数据表
IRFBE30S VISHAY

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