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SEMICONDUCTOR TECHNICAL DATA
Motorola Preferred Device
TMOS POWER FET
4.0 AMPERES
800 VOLTS
N–Channel Enhancement–Mode Silicon Gate
2
The D PAK package has the capability of housing a larger die
R
= 3.0 OHM
DS(on)
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower R
capabilities. This high voltage
DS(on)
MOSFET uses an advanced termination scheme to provide
enhanced voltage–blocking capability without degrading perfor-
mance over time. In addition, this advanced TMOS E–FET is
designed to withstand high energy in the avalanche and commuta-
tion modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
D
G
CASE 418B–02, Style 2
2
D PAK
•
•
•
Robust High Voltage Termination
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
S
•
•
•
•
•
Diode is Characterized for Use in Bridge Circuits
I
and V
Specified at Elevated Temperature
DSS
DS(on)
Short Heatsink Tab Manufactured — Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
Rating
Symbol
Value
800
Unit
Vdc
Vdc
Drain–Source Voltage
V
DSS
Drain–Gate Voltage (R
= 1.0 MΩ)
Gate–Source Voltage — Continuous
V
DGR
800
GS
V
± 20
± 40
Vdc
Vpk
GS
Gate–Source Voltage — Non–Repetitive (t ≤ 10 ms)
V
GSM
p
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (t ≤ 10 µs)
I
I
4.0
2.9
12
Adc
D
D
I
Apk
p
DM
Total Power Dissipation
Derate above 25°C
P
D
125
1.0
2.5
Watts
W/°C
Watts
Total Power Dissipation @ T = 25°C, when mounted with the minimum recommended pad size
A
Operating and Storage Temperature Range
T , T
stg
– 55 to 150
320
°C
J
Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C
E
AS
mJ
J
(V
DD
= 100 Vdc, V
= 10 Vdc, I = 8.0 Apk, L = 10 mH, R = 25 Ω)
GS L G
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size
R
θJC
R
θJA
R
θJA
1.0
62.5
50
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
T
L
260
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 4
Motorola TMOS Power MOSFET Transistor Device Data
1
Motorola, Inc. 1996