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MT9094AP PDF预览

MT9094AP

更新时间: 2024-01-16 09:25:00
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 电信电信集成电路
页数 文件大小 规格书
34页 572K
描述
Telecom Circuit, 1-Func, CMOS, PQCC44, PLASTIC, MS-018AC, LCC-44

MT9094AP 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:LPCC
针数:44Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.83
JESD-30 代码:S-PQCC-J44端子数量:44
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC44,.7SQ封装形状:SQUARE
封装形式:CHIP CARRIER电源:5 V
认证状态:Not Qualified子类别:Telephone Circuits
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD

MT9094AP 数据手册

 浏览型号MT9094AP的Datasheet PDF文件第2页浏览型号MT9094AP的Datasheet PDF文件第3页浏览型号MT9094AP的Datasheet PDF文件第4页浏览型号MT9094AP的Datasheet PDF文件第5页浏览型号MT9094AP的Datasheet PDF文件第6页浏览型号MT9094AP的Datasheet PDF文件第7页 
ISO2-CMOS ST-BUSFAMILY MT9094  
Digital Telephone (DPhone-II)  
ISSUE 2  
May 1995  
Features  
Ordering Information  
Programmable µ-Law/A-Law codec and filters  
Programmable CCITT (G.711)/sign-magnitude  
coding  
Programmable transmit, receive and side-tone  
gains  
DSP-based:  
MT9094AP  
44 Pin PLCC  
-40°C to +85°C  
Description  
i) Speakerphone switching algorithm  
ii) DTMF and single tone generator  
iii) Tone Ringer  
The MT9094 DPhone-II is a fully featured integrated  
digital telephone circuit. Voice band signals are  
converted to digital PCM and vice versa by a  
switched capacitor Filter/Codec. The Filter/Codec  
uses an ingenious differential architecture to achieve  
low noise operation over a wide dynamic range with  
a single 5V supply. A Digital Signal Processor  
provides handsfree speaker-phone operation. The  
DSP is also used to generate tones (DTMF, Ringer  
and Call Progress) and control audio gains. Internal  
registers are accessed through a serial microport  
conforming to INTEL MCS-51™ specifications. The  
device is fabricated in Zarlink's low power  
Differential interface to telephony transducers  
Differential audio paths  
Single 5 volt power supply  
Applications  
Fully featured digital telephone sets  
Cellular phone sets  
Local area communications stations  
2
ISO -CMOS technology.  
Digital Signal Processor  
Filter/Codec Gain  
MIC-  
DSTo  
7dB  
ENCODER  
DECODER  
22.5/-72dB  
MIC+  
1.5dB  
Transducer  
Interface  
DSTi  
-7dB  
Tx & Rx  
M-  
F0i  
M+  
C4i  
HSPKR+  
HSPKR-  
SPKR+  
SPKR-  
STATUS  
C-Channel  
Registers  
VSSD  
Control  
Registers  
VDD  
VSSA  
VSS  
New Call  
Tone  
SPKR  
Generator  
Timing  
Circuits  
VBias  
VRef  
DATA 2  
DATA 1  
SCLK  
CS  
Serial  
Port  
(MCS-51  
Compatible)  
S/P &  
P/S  
LCD Driver  
Converter  
S1  
S12  
BP  
WD PWRST IC  
Figure 1 Functional Block Diagram  
7-45  

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