Datasheet > MT90882BP1N

MT90882BP1N

更新时间： 2024-11-22 22:11:31

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		/
页数	文件大小	规格书
97页	695K
描述
TDM to Packet Processors

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数据手册

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MT90882BP1N 数据手册

MT90880/1/2/3

TDM to Packet Processors

Data Sheet

December 2004

Features

•

WAN interface, consisting of 32 input and output

streams at 2.048 or 8.192 Mbs

Ordering Information

•

Up to 1024 bi-directional 64 Kbs channels

MT90880B/IG/BP1N

456 ball PBGA

MT90881A/IG/BP1N

MT90882B/IG/BP1N

MT90883A/IG/BP1N

N * 64 Kbs trunking of channels across any

stream and channel

•

1 K by 1 K non-blocking TDM switch

Local TDM interface, with 32 streams at 2.048,

4.096 and 8.192 Mbs

-40°C to +85°C

•

Flexible, multi-protocol packet encapsulation

Dual 100 Mbs MII interfaces for redundancy or for

load balancing

Applications

•

Packet backplane interconnection

Circuit Emulation over packet domain

Internet Off-load

•

Quality of service features, including weighted fair

queuing, strict priority and queue size limit

thresholds

•

High performance 33 MHz / 66 MHz 32 bit PCI

bus

Remote Access Concentrators

H.100/H.110 extension and expansion

Integral Stratum 4E PLL for synchronisation to the

TDM domain

Power consumption of less than 0.75 W

Host Control/Data Interface

32 bit, 33MHz / 66MHz 32 PCI

WAN Access

Interface

Packet Switch

Fabric Interface

Administration

PCI Interface

1Kx1K TDM

Switch

Packetizing

and Circuit

Emulation

Dual Packet

Interface

MAC

TDM Re-

Formatter

Memory Manager

Packet Memory

Local TDM Interface

e.g. for connection to local resource pool 0.125 - 8 MBytes SSRAM

Figure 1 - MT90880 High Level Overview

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

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