Datasheet > MT90826

MT90826

更新时间： 2024-11-23 04:14:11

品牌	Logo	应用领域
MITEL		开关
页数	文件大小	规格书
30页	134K
描述
Quad Digital Switch

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MT90826 数据手册

MT90826

Quad Digital Switch

Advanced Information

DS5197

ISSUE 2

June 1999

Features

•

4,096 × 4,096 channel non-blocking switching

at 8.192 or 16.384 Mb/s

Ordering Information

Per-channel variable or constant throughput

delay

MT90826AL

MT90826AG

160 Pin MQFP

160 Pin PBGA

Accept ST-BUS streams of 2.048Mb/s,

4.096Mb/s, 8.192Mb/s, or 16.384 Mb/s

-40 to +85 C

Split Rate mode allows mix of two bit rates and

rate conversions

Automatic frame offset delay measurement for

ST-BUS input and output streams

Description

The MT90826 Quad Digital Switch has a non-

blocking switch capacity of 4,096 x 4,096 channels at

a serial bit rate of 8.192Mb/s or 16.384 Mb/s, 2,048 x

2,048 channels at 4.096Mb/s and 1024 x 1024

channels at 2.048Mb/s. The device has many

features that are programmable on a per stream or

per channel basis, including message mode, input

offset delay and high impedance output control.

•

Per-stream frame delay offset programming

Per-channel high impedance output control

Bit Error Monitoring on selected ST-BUS input

and output channels.

•

Per-channel message mode

Connection memory block programming

IEEE-1149.1 (JTAG) Test Port

3.3V local I/O with 5V tolerant inputs and TTL

compatible outputs

The per stream input and output delay control is

particularly useful for managing large multi-chip

switches with a distributed backplane.

Applications

•

Medium and large switching platforms

CTI application

Operating in Split Rate mode allows for switching

between two groups of bit rate streams.

Voice/data multiplexer

Digital cross connects

WAN access system

Wireless base stations

ODE

TMS TDI TDO TCK TRST IC1 RESET

Test Port

Parallel

Serial

STi0/FEi0

STi1/FEi1

STo0

STo1

•

Output

MUX

Multiple Buffer

Data Memory

•

Serial

Parallel

Converter

•

Converter

STi31/FEi31

STo31

Connection

Internal

Registers

Memory

Timing

Unit

Microprocessor Interface

PLLV

CLK F0i IC2 IC3 DT1 AT1

DS CS R/W A13-A0 DTA

D15-D0

Figure 1 - Functional Block Diagram

12 3 4 5 6 7...30

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