CMOS ST-BUSTM Family MT9079
Advanced Controller for E1
Data Sheet
July 2005
Features
•
Meets applicable requirements of CCITT
Ordering Information
G.704, G.706, G.732, G.775, G.796, I.431 and
MT9079AE
MT9079AL
MT9079AP
MT9079APR
MT9079AP1
40 Pin PDIP
44 Pin QFP
44 Pin PLCC
44 Pin PLCC
44 Pin PLCC*
Tubes
ETSI ETS 300 011
HDB3, RZ, NRZ (fibre interface) and bipolar
NRZ line codes
Trays
Tubes
•
•
•
•
Tape & Reel
Tubes
Data link access and national bit buffers (five
MT9079APR1 44 Pin PLCC*
*Pb Free Matte Tin
Tape & Reel
bytes each)
-40°C to +85°C
Enhanced alarms, performance monitoring and
error insertion
Maskable interrupts for alarms, receive CAS bit
changes, exception conditions and counter
overflows
•
•
•
CO and PABX switching equipment interfaces
E1 add/drop multiplexers and channel banks
Test equipment and satellite interfaces
•
•
•
Automatic interworking between CRC-4 and
non-CRC-4 multiframing
Description
The MT9079 is a feature rich E1 (PCM 30, 2.048
Mbps) link framer and controller that meets the latest
CCITT and ETSI requirements.
Dual transmit and receive 16 byte circular
channel buffers
Two frame receive elastic buffer with controlled
slip direction indication and 26 channel
hysteresis (208 UI wander tolerance)
The MT9079 will interface to a 2.048 Mbps backplane
and can be controlled directly by a parallel processor,
serial controller or through the ST-BUS.
•
CRC-4 updating algorithm for intermediate path
points of a message-based data link application
Extensive alarm transmission and reporting, as well as
exhaustive performance monitoring and error
diagnostic features make this device ideal for a wide
variety of applications.
Applications
•
•
Primary rate ISDN network nodes
Digital Access Cross-connect (DACs)
TxMF
TAIS
Transmit & Receive
Frame MUX/DEMUX
PCM 30
TxA
RxMF
DSTi
DSTo
Data
(E1)
TxB
2 Frame Rx
Elastic
Interface
Link
Interface
RxA
RxB
Buffer With
Slip Control
TxDL
RxDL
DLCLK
Data
Link
Dual 16
Dual 16
Byte Rx
Buffer
National
Bit
Byte Tx
Buffer
Buffer
Buffer
Performance
Monitoring &
Alarm
E2i
÷
Test
Code
Gen.
256
E8Ko
Control
ABCD
Control
Signal
Buffer
Control
Port
Interface
(fig. 3)
Circuit
Timing
Interface
Phase
Detector
V
SS
IC
DD
V
C4i/C2i
F0i
to all registers
and counters
Circuit
Timing
ST-BUS Timing
RESET
Figure 1 - Functional Block Diagram
1
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