Datasheet > MT9079AL

MT9079AL

更新时间： 2024-11-01 10:43:47

品牌	Logo	应用领域
MITEL		电信集成电路控制器
页数	文件大小	规格书
54页	569K
描述
CMOS ST-BUS? FAMILY Advanced Controller for E1

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MT9079AL 数据手册

CMOS ST-BUS FAMILY MT9079

Advanced Controller for E1

ISSUE 2

May 1995

Features

•

Meets applicable requirements of CCITT

G.704, G.706, G.732, G.775, G.796, I.431 and

ETSI ETS 300 011

Ordering Information

MT9079AC

40 Pin Ceramic DIP

40 Pin Plastic DIP

44 Pin QFP

MT9079AE

MT9079AL

MT9079AP

•

HDB3, RZ, NRZ (fibre interface) and bipolar

NRZ line codes

44 Pin PLCC

Data link access and national bit buffers (five

bytes each)

-40° to 85°C

Enhanced alarms, performance monitoring and

error insertion

Description

The MT9079 is a feature rich E1 (PCM 30, 2.048

Mbps) link framer and controller that meets the latest

CCITT and ETSI requirements.

Maskable interrupts for alarms, receive CAS bit

changes, exception conditions and counter

overflows

•

Automatic interworking between CRC-4 and

non-CRC-4 multiframing

The MT9079 will interface to

a 2.048 Mbps

backplane and can be controlled directly by a

parallel processor, serial controller or through the

ST-BUS.

Dual transmit and receive 16 byte circular

channel buffers

Two frame receive elastic buffer with controlled

slip direction indication and 26 channel

hysteresis (208 UI wander tolerance)

Extensive alarm transmission and reporting, as well

as exhaustive performance monitoring and error

diagnostic features make this device ideal for a wide

variety of applications.

•

CRC-4 updating algorithm for intermediate path

points of a message-based data link application

Applications

•

Primary rate ISDN network nodes

Digital Access Cross-connect (DACs)

CO and PABX switching equipment interfaces

E1 add/drop multiplexers and channel banks

Test equipment and satellite interfaces

TxMF

RxMF

TAIS

Transmit & Receive

PCM 30

TxA

TxB

Frame MUX/DEMUX

DSTi

DSTo

Data

Interface

(E1)

2 Frame Rx

Elastic

Buffer With

Slip Control

Link

RxA

RxB

Interface

TxDL

RxDL

DLCLK

Data

Link

Buffer

Dual 16

Byte Tx

Buffer

Dual 16

Byte Rx

Buffer

National

Bit

Buffer

Performance

Monitoring &

Alarm

E2i

Test

Code

Gen.

256

E8Ko

Control

ABCD

Signal

Buffer

Control

Interface

Port

Interface

(fig. 3)

Circuit

Timing

Phase

Detector

C4i/C2i

F0i

to all registers

and counters

Circuit

Timing

ST-BUS Timing

RESET

Figure 1 - Functional Block Diagram

4-237

12 3 4 5 6 7...54

中文翻译

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