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MT9076BP PDF预览

MT9076BP

更新时间: 2024-02-29 22:32:06
品牌 Logo 应用领域
加拿大卓联 - ZARLINK /
页数 文件大小 规格书
172页 1213K
描述
T1/E1/J1 3.3 V Single Chip Transceiver

MT9076BP 技术参数

是否Rohs认证: 不符合生命周期:Contact Manufacturer
零件包装代码:LCC包装说明:QCCJ, LDCC68,1.0SQ
针数:68Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.25
运营商类型:CEPT PCM-30/E-1运营商类型(2):T-1(DS1)
JESD-30 代码:S-PQCC-J68端子数量:68
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC68,1.0SQ封装形状:SQUARE
封装形式:CHIP CARRIER电源:3.3 V
认证状态:Not Qualified子类别:Other Telecom ICs
最大压摆率:0.098 mA标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:FRAMER
温度等级:INDUSTRIAL端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
Base Number Matches:1

MT9076BP 数据手册

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MT9076B  
T1/E1/J1 3.3 V Single Chip Transceiver  
Data Sheet  
December 2005  
Features  
Combined T1/E1/J1 framer and LIU, with PLL and  
Ordering Information  
3 HDLCs  
MT9076BP  
MT9076BB  
68 Pin PLCC  
80 Pin LQFP  
Tubes  
In T1/J1 mode the LIU can recover signals  
attenuated by up to 36 dB (at 772 kHz)  
In E1 mode the LIU can recover signals  
attenuated by up to 40 dB (at 1.024 MHz)  
Trays  
MT9076BPR 68 Pin PLCC  
Tape & Reel  
Trays  
MT9076BB1  
MT9076BP1  
80 Pin LQFP*  
68 Pin PLCC*  
Tubes  
*Pb Free Matte Tin  
Low jitter digital PLL (intrinsic jitter < 0.02UI)  
HDLCs can be assigned to any timeslot  
-40°C to +85°C  
Applications  
Comprehensive alarm detection, performance  
monitoring and error insertion functions  
T1/E1/J1 add/drop multiplexers  
Access networks  
2.048 Mbit/s or 8.192 Mbit/s ST-BUS streams  
Support for Inverse Mux for ATM (IMA)  
Support for V5.1 and V5.2 Access Networks  
3.3 V operation with 5 V tolerant inputs  
Wireless base stations  
CO and CPE equipment interfaces  
Primary rate ISDN nodes  
Intel or Motorola non-multiplexed 8-bit  
microprocessor port  
Digital Cross-connect Systems (DCS)  
JTAG boundary scan  
TxDL TxDLCLK  
TxMF  
TxAO TxB TxA  
DSTi  
CSTi  
ST-BUS  
Interface  
Transmit Framing, Error,  
Line  
TTIP  
Test Signal Generation and Slip Buffer  
Driver  
TRING  
Tdi  
Tdo  
PL Loop  
Tms  
Tclk  
Trst  
ST Loop  
National  
Bit Buffer  
S/FR  
Jitter Attenuator  
& Clock Control  
IRQ  
BS/LS  
OSC1  
OSC2  
D7~D0  
Data Link,  
HDLC0  
HDLC1  
CAS  
AC4  
Buffer  
AC0  
DG Loop  
R/W/WR  
CS  
RTIP  
DS/RD  
RRING  
DSTo  
CSTo  
Receive Framing, Performance Monitoring,  
Alarm Detection, 2 Frame Slip Buffer  
ST-BUS  
Interface  
RxDLCLK RxDL  
RxMF/TxFP  
LOS  
RxFP  
Exclk F0b C4b  
Figure 1 - MT9076 Functional Block  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2002-2005, Zarlink Semiconductor Inc. All Rights Reserved.  

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