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MT9075BP1 PDF预览

MT9075BP1

更新时间: 2024-01-08 02:42:56
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 数字传输控制器电信集成电路电信电路PC
页数 文件大小 规格书
102页 867K
描述
E1 Single Chip Transceiver

MT9075BP1 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:QCCJ,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.59
Is Samacsys:NJESD-30 代码:S-PQCC-J68
JESD-609代码:e3长度:24.23 mm
湿度敏感等级:3功能数量:1
端子数量:68最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:4.57 mm
标称供电电压:5 V表面贴装:YES
电信集成电路类型:FRAMER温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:24.23 mm
Base Number Matches:1

MT9075BP1 数据手册

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MT9075B  
E1 Single Chip Transceiver  
Data Sheet  
August 2005  
Features  
Combined PCM 30 framer, Line Interface Unit  
Ordering Information  
(LIU) and link controllers in a 68 pin PLCC or 100  
pin MQFP package  
MT9075BPR  
MT9075BL  
MT9075BP  
68 Pin PLCC  
100 Pin MQFP Trays  
68 Pin PLCC Tubes  
Tape & Reel  
Selectable bit rate data link access with optional  
Sa bits HDLC controller (HDLC0) and channel 16  
HDLC controller (HDLC1)  
MT9075BPR1 68 Pin PLCC* Tape & Reel  
MT9075BP1  
MT9075BL1  
68 Pin PLCC* Tubes  
100 Pin MQFP* Trays  
*Pb Free Matte Tin  
LIU dynamic range of 20 dB  
Enhanced performance monitoring and  
programmable error insertion functions  
-40°C to +85°C  
Low jitter DPLL for clock generation  
Operating under synchronized or free run mode  
Applications  
Two-frame receive elastic buffer with controlled  
slip direction indication  
E1 add/drop multiplexers and channel banks  
CO and PBX equipment interfaces  
Primary Rate ISDN nodes  
Digital Cross-connect Systems (DCS)  
Selectable transmit or receive jitter attenuator  
Intel or Motorola non-multiplexed parallel  
microprocessor interface  
CRC-4 updating algorithm for intermediate path  
points of a message-based data link application  
ST-BUS/GCI 2.048 Mbit/s backplane bus for both  
data and signalling  
TxDL TxDLCLK  
TxMF  
TAIS  
DSTi  
CSTi  
ST-BUS  
Interface  
Transmit Framing, Error and  
Test Signal Generation  
TTIP  
Line  
Driver  
TRING  
Tdi  
Tdo  
Tms  
Tclk  
Trst  
PL Loop  
ST Loop  
National  
Bit Buffer  
BL/FR  
INT/MOT  
Jitter Attenuator  
& Clock Control  
BS/LS  
OSC1  
OSC2  
IRQ  
D7~D0  
Data Link,  
HDLC0,  
HDLC1  
CAS  
AC4  
Buffer  
~AC0  
DG Loop  
R/W/WR  
CS  
RTIP  
DS/RD  
RRING  
DSTo  
CSTo  
Receive Framing, Performance Monitoring,  
Alarm Detection, 2 Frame Slip Buffer  
ST-BUS  
Interface  
RxDLCLK RxDL RxMF  
LOS  
RxFP/Rx64kCK  
E2o F0b C4b  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2002-2005, Zarlink Semiconductor Inc. All Rights Reserved.  

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