Datasheet > MT9075A

MT9075A

更新时间： 2024-09-22 22:45:51

品牌	Logo	应用领域
MITEL		/
页数	文件大小	规格书
78页	939K
描述
E1 Single Chip Transceiver

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MT9075A 数据手册

MT9075A

E1 Single Chip Transceiver

Preliminary Information

ISSUE 5

December 1997

Features

•

Combined PCM 30 framer, Line Interface Unit

(LIU) and link controllers in a 68 pin PLCC or

100 pin MQFP package

Ordering Information

MT9075AP

MT9075AL

68Pin PLCC

100 Pin MQFP

Selectable bit rate data link access with

-40°C to 85°C

optional S bits HDLC controller (HDLC0) and

channel 16 HDLC controller (HDLC1)

Description

Enhanced performance monitoring and

programmable error insertion functions

The MT9075A is a single chip device which

integrates an advanced PCM 30 framer with a Line

Interface Unit (LIU).

•

Low jitter DPLL for clock generation

Operating under synchronized or free run mode

Two-frame receive elastic buffer with controlled

slip direction indication

The framer interfaces to a 2.048 Mbit/s backplane

and provides selectable rate data link access with

•

Selectable transmit or receive jitter attenuator

Intel or Motorola non-multiplexed parallel

microprocessor interface

optional HDLC controllers for S bits and channel 16.

The LIU interfaces the framer functions to the PCM

30 transformer-isolated four wire line.

•

CRC-4 updating algorithm for intermediate path

points of a message-based data link application

ST-BUS/GCI 2.048 Mbit/s backplane bus for

both data and signalling.

The MT9075A meets or supports the latest ITU-T

Recommendations including G.703, G.704, G.706,

G.732, G.775, G.796, G.823 for PCM 30, and I.431

for ISDN primary rate. It also meets or supports ETSI

ETS 300 166 and BS 6450.

Applications

•

E1 add/drop multiplexers and channel banks

CO and PBX equipment interfaces

Primary Rate ISDN nodes

Digital Cross-connect Systems (DCS)

TxDL TxDLCLK

TxMF

TAIS

DSTi

CSTi

ST-BUS

Interface

Transmit Framing, Error and

Test Signal Generation

TTIP

TRING

Line

Driver

Tdi

Tdo

Tms

Tclk

Trst

PL Loop

ST Loop

National

Bit Buffer

MS/FR

Jitter Attenuator

& Clock Control

IRQ

M/S

OSC1

OSC2

D7~D0

Data Link,

CAS

Buffer

AC4

HDLC0,

HDLC1

~AC0

DG Loop

R/W/WR

DS/RD

RTIP

RRING

DSTo

CSTo

Receive Framing, Performance Monitoring,

Alarm Detection, 2 Frame Slip Buffer

ST-BUS

Interface

RxDLCLK RxDL RxMF

LOS

RxFP/Rx64kCK

E2o F0b C4b

Figure 1 - Functional Block Diagram

4-129

12 3 4 5 6 7...78

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与MT9075A相关器件

型号	品牌	获取价格	描述	数据表
MT9075AL	MITEL	获取价格	E1 Single Chip Transceiver
MT9075AP	MITEL	获取价格	E1 Single Chip Transceiver
MT9075B	MITEL	获取价格	E1 Single Chip Transceiver
MT9075B	ZARLINK	获取价格	E1 Single Chip Transceiver
MT9075B-1	MITEL	获取价格	E1 Single Chip Transceiver
MT9075BL	ZARLINK	获取价格	E1 Single Chip Transceiver
MT9075BL	MITEL	获取价格	E1 Single Chip Transceiver
MT9075BL1	ZARLINK	获取价格	E1 Single Chip Transceiver
MT9075BP	ZARLINK	获取价格	E1 Single Chip Transceiver
MT9075BP	MITEL	获取价格	E1 Single Chip Transceiver