Datasheet > MT90733AP

MT90733AP

更新时间： 2024-09-22 22:45:51

品牌	Logo	应用领域
MITEL		电信集成电路
页数	文件大小	规格书
8页	56K
描述
CMOS DS3 Framer (DS3F)

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数据手册

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MT90733AP 数据手册

CMOS

MT90733

DS3 Framer (DS3F)

Advance Information

ISSUE 1

May 1995

Features

•

DS3 payload access in either bit-serial or

nibble-parallel mode

Ordering Information

MT90733AP

68 Pin PLCC

-40° to 85°C

•

C-bit parity or M13 operating mode

Separate interface for C-bits

Description

Detect and generate DS3 AIS, and idle signals

The MT90733 DS3 Framer (DS3F) is designed for

mapping broadband payloads into the DS3 frame for-

mat, which meets ANSI’s T1.107-1988 and supple-

ment T1.107a-1990.

Transmit reference generator for serial

operation

•

Transmit and receive FEAC channel under

software control

Transmit single errors: framing, FEBE, C-bit

parity, and P-bit parity

Although the C-bit parity format is recommended, the

DS3F can also operate in the M13 mode. In the C-bit

parity format, the DS3F provides a separate interface

for selected C-bits. The DS3F also provides software

access for transmitting and receiving the FEAC chan-

nel, and generates and detects DS3 AIS, DS3 idle, P-

bit parity and C-bit parity. In addition, performance

counters are provided, as well as the ability to gener-

ate single framing, FEBE, C-bit parity and P-bit parity

errors. The payload interface is selectable through

software as either a bit-serial or nibble-parallel format.

•

FEBE, C-bit and P-bit performance counters

Transmit-to-Receive and Receive-to-Transmit

loopbacks

Applications

•

Subrate multiplexing

Wideband data or video transport

DS3 monitor and test

Channel extenders

Terminal Side

Line Side

Receive

Serial Parallel

N.C. RNIB3

DS3

Interpreter

D3RD

D3RC

DS3

Receive

N.C. RNIB2

N.C. RNIB1

RDS RNIB0

RCS RCN

RCG N.C.

RFS RFN

CRD

CRCK

CRF

CRDCC

STUFC

STUFD

Output

TDOUT

TCG

TFOUT

TCOUT

TFIN

AD(7-0)

Transmit

Frame

Reference

Generator

ALE

SEL

µP I/O

TCIN

OENA

FORCEOE

CXD

N.C. XFNO

N.C. XCN

XCK XCK

XFSI N.C.

XDS XNIB3

N.C. XNIB2

N.C. XNIB1

N.C. XNIB0

CXCK

CXF

CXDCC

Input

DS3

Send

D3TD

D3TC

FORCECP

FORCEPP

FORCFEBE

Transmit

Figure 1 - Functional Block Diagram

U.S. Patent Number 5040170

5-23

12 3 4 5 6 7 8

中文翻译

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