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MT90732 PDF预览

MT90732

更新时间: 2024-09-22 22:45:51
品牌 Logo 应用领域
MITEL /
页数 文件大小 规格书
8页 65K
描述
CMOS E2/E3 Framer (E2/E3F)

MT90732 数据手册

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MT90732  
CMOS  
E2/E3 Framer (E2/E3F)  
Advance Information  
ISSUE 1  
May 1995  
Features  
Framer for CCITT Recommendations  
Ordering Information  
- G.742 (8448 kbit/s)  
- G.745 (8448 kbit/s)  
- G.751 (34368 kbit/s)  
- G.753 (34368 kbit/s)  
MT90732AP  
68 Pin PLCC  
-40°C to +85°C  
Description  
The MT90732 E2/E3 Framer (E2/E3F) is a CMOS  
VLSI device that provides the functions needed to  
frame a wideband payload to one of four CCITT  
Recommendations. G.742, G.745, G.751, or G.753.  
The E2/E3 Framer interfaces to line circuitry with  
either dual rail or NRZ signals. On the terminal side,  
the interface can be either nibble-parallel or bit-  
serial.  
Line side interface  
- Dual rail or NRZ  
HDB3 codec for dual rail I/O  
Terminal side interface  
- Nibble-parallel  
- Bit-serial  
Transmit reference generator for bit-serial I/O  
Microprocessor or control leads  
I/O port for service bits  
The MT90732 can be operated with or without a  
microprocessor.  
When  
interfaced  
with  
a
microprocessor, the E2/E3 Framer provides an 8-  
byte memory map for control, performance counters  
and alarm status. The MT90732 provides a transmit  
and receive interface port for accessing the  
Applications  
Line terminals  
Wideband data or video transport  
Test equipment  
overhead  
bits  
from  
each  
of  
the  
four  
recommendations. The overhead bits can also be  
accessed by the microprocessor via the memory  
map.  
Multiplexer systems  
RDL  
RCKL  
SERIAL  
PARALLEL  
Data  
RSD  
TDOUT  
TCG  
TFOUT  
RSC  
RSF  
RCG  
RNIB3  
RNIB2  
RNIB1  
RNIB0  
RNC  
RNF  
N.C.  
Data  
Clock  
Frame  
Data  
RP/RDL  
Clock  
Frame  
Line  
Decoder  
RN  
RCK/RCKL  
CV  
Interpreter  
Framer  
Clock  
Output  
RAIS  
RLOC  
BIP-4E  
AD7  
AD6  
AD5  
AD4  
AD3  
AD2  
AD1  
AD0  
SEL  
ALE  
RD  
WR  
RDY  
RLOF  
ROD  
ROC  
ROF  
Micro-  
processor  
I/O  
FE  
NRZ LINE  
BIP-4  
M0  
M1  
MICRO  
SER  
Control  
DAIS  
TLBK  
PLBK  
TAIS  
LPT  
TLCINV  
TLOC  
Transmit  
Reference  
Generator  
FORCEFE  
TOD  
XSF  
N.C.  
TCIN  
XSD  
XNIB3  
XNIB2  
XNIB1  
XNIB0  
TOC  
TOF  
RESET  
TP/TDL  
TCK/TCKL  
TCKL  
TDL  
Input  
Clock  
Data  
Framing  
XCK  
XNF  
XNC  
XCK  
N.C.  
TCOUT  
Data  
Clock  
G.7XX  
Send  
Line  
Encoder  
TN  
Line Side  
Terminal Side  
Figure 1 - Functional Block Diagram  
U.S. Patent Number 5040170  
5-15  

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