MT9072AV

更新时间： 2024-02-04 12:14:29

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		数字传输控制器电信集成电路电信电路
页数	文件大小	规格书
275页	3569K
描述
Octal T1/E1/J1 Framer

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技术参数
数据手册

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MT9072AV 技术参数

是否无铅：	含铅	生命周期：	Transferred
零件包装代码：	BGA	包装说明：	,
针数：	220	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.31
JESD-30 代码：	S-PBGA-B256	功能数量：	8
端子数量：	256	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装形状：	SQUARE	封装形式：	GRID ARRAY
认证状态：	Not Qualified	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	FRAMER
温度等级：	INDUSTRIAL	端子形式：	BALL
端子位置：	BOTTOM	Base Number Matches：	1

MT9072AV 数据手册

MT9072

Octal T1/E1/J1 Framer

Data Sheet

October 2004

Features

•

Eight fully independent, T1/E1/J1 framers

3.3 V supply with 5 V tolerant inputs

Ordering Information

Selectable 2.048 Mbit/s or 8.192 Mbit/s serial

MT9072AB

MT9072AV

208 Pin LQFP

220 Pin LBGA

buses for both data and signaling

•

Framing Modes:

- T1: D4, ESF, T1DM

-40°C to +85°C

- E1: Basic Framing, CRC4 multiframing and

•

Digital Cross-connect Systems (DCS)

Wireless base stations

Signaling Multiframing

•

Supports Inverse Mux for ATM

Timeslot assignable HDLC

IEEE-1149.1 (JTAG) test port

Description

The MT9072 is a multi-port T1/E1/J1 framing device

that integrates eight fully independent, feature rich

framers. The device is software selectable between T1,

E1 or J1 modes and meets the latest relevant

recommendations and standards from Telcordia, ANSI,

ETSI and ITU-T. An extensive suite of features make

the MT9072 very flexible and suitable for a wide variety

of applications around the globe.

Applications

•

T1/E1/J1 add/drop multiplexers

V5.1 and V5.2 access network interfaces

CO and PBX equipment interfaces

Primary rate IDSN nodes

TxDL[0] TxDLC[0]

TxCL [0]

DSTi [0]

CSTi [0]

TPOS[0]

TNEG[0]

ST-BUS

Transmit Framing, Error and

Interface

Test Signal Generation

Remote

Payload

ST-BUS

Loopback

National

Bit Buffer

CKi[0]

FPi[0]

ST-BUS

CAS

Data Link

Buffer

Digital

Loopback

Circuit

Timing

DSTo[0]

CSTo[0]

RPOS[0]

RNEG[0]

Receive Framing, Performance Monitoring,

Alarm Detection, 2 Frame Slip Buffer

ST-BUS

Interface

RxDLC[0] RxDL[0] RxMF[0]

RxBF[0] EXCLi[0]

FRAMER 0

FRAMER 1

FRAMER 2

FRAMER 3

FRAMER 4

FRAMER 5

FRAMER 6

FRAMER 7

Microprocessor Interface

Common Control and Power

IEEE 1149.1 TAP

D15~D0 A11~A0

DS RW CS IRQ IM

TDI TDO TMSTCK TRST RESET TAIS VDDVSS T1-3 TxMF

Figure 1 - Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

12 3 4 5 6 7...275

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