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MT90502_06 PDF预览

MT90502_06

更新时间: 2024-02-01 10:15:19
品牌 Logo 应用领域
加拿大卓联 - ZARLINK /
页数 文件大小 规格书
205页 1551K
描述
Multi-Channel AAL2 SAR

MT90502_06 数据手册

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MT90502  
Multi-Channel AAL2 SAR  
Data Sheet  
May 2006  
Features  
AAL2 Segmentation Reassembly device  
Ordering Information  
capable of simultaneously processing up to  
1023 active CIDs (AAL2 Channel Identifier) and  
1023 active VCs (Virtual Circuits)  
MT90502AG  
456 PBGA  
Trays  
Trays  
MT90502AG2 456 PBGA**  
**Pb Free Tin/Silver/Copper  
Support for up to 255 CIDs per VC. Maximum of  
1023 CIDs  
0 to +70°C  
Implements AAL2 Common Part Sub-layer  
(CPS) functions specified in ITU I.363.2  
TDM bus also supports compressed voice such  
as ITU G.723, G.728 and G.729 through HDLC  
encapsulation  
Implements AAL2 Service Specific  
Convergence Sub-layer (SSCS) functions for  
G.711 PCM and G.726 ADPCM voice  
Three UTOPIA Level 1 ports configurable as  
PHY or ATM allowing for connection to an  
external AAL5 SAR processor, or for chaining  
multiple MT90502 devices. Ports A & B are  
configurable as a single 8-bit UTOPIA Level 2  
PHY port with 5 ADDR lines  
Supports 44-byte PCM or ADPCM packet  
profiles specified in AF-VMOA-0145.00  
CPS packet payload can support up to 64-bytes  
Supports over-subscription of 10:1  
H.100/H.110 compatible TDM bus for PCM or  
ADPCM data. Supports both master and slave  
TDM bus clock operation  
UTOPIA module provides a cell switching  
function with a header translation  
Performs silence suppression for PCM and  
ADPCM  
Memory Bank A  
Memory Bank B (Optional)  
SSRAM  
(max: 1M x18)  
SDRAM  
(max: 8M x16)  
SSRAM  
(max: 1M x18)  
SDRAM  
(max: 8M x16)  
MT90502  
Dual Memory Controller  
UTOPIA  
Module  
TDM Bus  
4096 x 64 kbps  
RxA Port  
TxA Port  
Port  
A
RX  
AAL2 SAR  
Receiver  
CPS Packets  
TDM  
Module  
RxB Port  
TxB Port  
Port  
B
AAL2 SAR  
Transmitter  
TX  
Clock and  
Frame  
Pulse  
CPS Packets  
RxC Port  
TxC Port  
Port  
C
Clock  
Recovery  
and  
JTAG Interface  
CPU Interface  
Generation  
Figure 1 - MT90502 Functional Block  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2001-2005, Zarlink Semiconductor Inc. All Rights Reserved.  

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