Datasheet > MT90500

MT90500

更新时间： 2024-09-22 22:45:51

品牌	Logo	应用领域
MITEL		异步传输模式 ATM
页数	文件大小	规格书
159页	511K
描述
Multi-Channel ATM AAL1 SAR

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中文翻译

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数据手册

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MT90500 数据手册

MT90500

Multi-Channel ATM AAL1 SAR

DS5171

ISSUE 4

April 1999

Features

•

AAL1 Segmentation and Reassembly device

compatible with Structured Data Transfer (SDT)

as per ANSI T1.630 and ITU I.363 standards

Ordering Information

MT90500AL

240 Pin Plastic QFP

•

Transports 64kbps and N x 64kbps trafﬁc over

ATM AAL1 cells (also over AAL5 or AAL0)

-40 to +85 C

Simultaneous processing of up to 1024

bidirectional Virtual Circuits

streams at 2.048, 4.096, or 8.192 Mbps for up

to 2048 TDM 64 kbps channels

Flexible aggregation capabilities (Nx64) to

allow any combination of 64 kbps channels

while maintaining frame integrity (DS0

grooming)

•

Compatible with ST-BUS, MVIP, H-MVIP and

SCSA interfaces

Supports master and slave TDM bus clock

operation

•

Support for clock recovery - Adaptive Clock

Recovery, Synchronous Residual Time Stamp

(SRTS), or external

•

Loopback function at TDM bus interface

Local TDM bus provides clocks, input pin and

output pin for 2.048 Mbps operation

Primary UTOPIA port (Level 1, 25 MHz) for

connection to external PHY devices with data

throughput of up to 155 Mbps

•

Master clock rate up to 60 MHz

Dual rails (3.3V for power minimization, 5V for

standard I/O)

Secondary UTOPIA port for connection to an

external AAL5 SAR processor, or for chaining

multiple MT90500 devices

•

IEEE1149 (JTAG) interface

•

16-bit microprocessor port, conﬁgurable to

Motorola or Intel timing

TDM bus provides 16 bidirectional serial TDM

TX / RX

Control Structures

and Circular Buffers

Lookup

Tables

External

Synchronous

SRAM

TDM Bus

16 Lines

TDM Module

External Memory Controller

2048 x 64 kbps

(max.)

TDM Bus

Interface

Local TDM Bus

32 x 64 kbps in

32 x 64 kbps out

Internal

TDM

Clock

Logic

UTOPIA

MUX

To/From

External

PHY

Main

UTOPIA

Interface

TDM

AAL1

SAR

Clock Signals

Frame

Buffer

Clock

Recovery

AAL1

SAR

UTOPIA

Registers

UTOPIA Module

From

Secondary

UTOPIA

Microprocessor

Interface

Boundary Scan

External

ATM SAR Interface

16-bit Microprocessor Address

and Data Buses

JTAG

Interface

Figure A - MT90500 Block Diagram

12 3 4 5 6 7...159

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与MT90500相关器件

型号	品牌	获取价格	描述	数据表
MT90500AL	MITEL	获取价格	Multi-Channel ATM AAL1 SAR
MT90500AL	ZARLINK	获取价格	ATM Segmentation and Reassembly Device, 1-Func, PQFP240, 32 X 32 MM, 3.40 MM HEIGHT, PLAST
MT90502	ZARLINK	获取价格	Multi-Channel AAL2 SAR
MT90502_06	ZARLINK	获取价格	Multi-Channel AAL2 SAR
MT90502AG	ZARLINK	获取价格	Multi-Channel AAL2 SAR
MT90503	ZARLINK	获取价格	2048VC AAL1 SAR
MT90503AG	ZARLINK	获取价格	2048VC AAL1 SAR
MT90503AG	MICROSEMI	获取价格	ATM SEGMENTATION AND REASSEMBLY DEVICE, PBGA503, 40 X 40 MM, 2.33 MM HEIGHT, PLASTIC, MS-0
MT90520	ZARLINK	获取价格	8-Port Primary Rate Circuit Emulation AAL1 SAR
MT90520AG	ZARLINK	获取价格	8-Port Primary Rate Circuit Emulation AAL1 SAR