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MT9045AN PDF预览

MT9045AN

更新时间: 2024-01-16 13:59:56
品牌 Logo 应用领域
加拿大卓联 - ZARLINK /
页数 文件大小 规格书
34页 479K
描述
T1/E1/OC3 System Synchronizer

MT9045AN 技术参数

是否无铅: 含铅生命周期:Obsolete
零件包装代码:SSOP包装说明:,
针数:48Reach Compliance Code:compliant
风险等级:5.81

MT9045AN 数据手册

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MT9045  
T1/E1/OC3 System Synchronizer  
Data Sheet  
November 2003  
Features  
Supports AT&T TR62411 and Bellcore GR-1244-  
CORE Stratum 3, Stratum 4 Enhanced and  
Stratum 4 timing for DS1 interfaces  
Ordering Information  
MT9045AN 48 pin SSOP  
Supports ITU-T G.813 Option 1 clocks for 2048  
kbit/s interfaces  
-40°C to +85°C  
Supports ITU-T G.812 Type IV clocks for 1,544  
kbit/s interfaces and 2,048 kbit/s interfaces  
Provides Time Interval Error (TIE) correction  
Supports ETSI ETS 300 011, TBR 4, TBR 12 and  
TBR 13 timing for E1 interfaces  
Accepts reference inputs from two independent  
sources  
Selectable 19.44 MHz, 1.544MHz, 2.048MHz or  
8kHz input reference signals  
JTAG Boundary Scan  
Provides C1.5, C2, C4, C6, C8, C16, and C19  
(STS-3/OC3 clock divided by 8) output clock  
signals  
Applications  
Synchronization and timing control for multitrunk  
T1,E1 and STS-3/OC3 systems  
Provides 5 styles of 8 KHz framing pulses  
Holdover frequency accuracy of 0.05 PPM  
Holdover indication  
ST-BUS clock and frame pulse sources  
Attenuates wander from 1.9Hz  
Fast lock mode  
TCLR  
OSCi  
OSCo  
LOCK  
VDD  
VSS  
Virtual  
Reference  
Master Clock  
C19o  
C1.5o  
C2o  
C4o  
C6o  
C8o  
C16o  
F0o  
F8o  
F16o  
RSP  
TIE  
Corrector  
Circuit  
TCK  
TDI  
TMS  
TRST  
TDO  
DPLL  
IEEE  
1149.1a  
Output  
Interface  
Circuit  
Selected  
State  
Select  
Reference  
Reference  
Select  
PRI  
SEC  
Input  
Impairment  
Monitor  
MUX  
TIE  
Corrector  
Enable  
State  
Select  
Prioor  
Secoor  
Reference  
Monitor  
TSP  
Reference  
Select  
Frequency  
Select  
MUX  
RSEL  
Control State Machine  
Feedback  
MS1 MS2  
RST HOLDOVER PCCi FLOCK  
FS1  
FS2  
Figure 1 - Functional Block Diagram  
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,  
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.  

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