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MT9044APR PDF预览

MT9044APR

更新时间: 2024-02-25 05:34:46
品牌 Logo 应用领域
美高森美 - MICROSEMI PC
页数 文件大小 规格书
39页 500K
描述
Telecom IC, CMOS, PQCC44

MT9044APR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QCCJ, LDCC44,.7SQReach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.7
JESD-30 代码:S-PQCC-J44JESD-609代码:e0
长度:16.585 mm湿度敏感等级:1
功能数量:1端子数量:44
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC44,.7SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):225
电源:5 V认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Other Telecom ICs
标称供电电压:5 V表面贴装:YES
技术:CMOS电信集成电路类型:TELECOM CIRCUIT
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:16.585 mmBase Number Matches:1

MT9044APR 数据手册

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MT9044  
T1/E1/OC3 System Synchronizer  
Data Sheet  
November 2005  
Features  
Supports AT&T TR62411 and Bellcore GR-1244-  
CORE Stratum 3, Stratum 4 Enhanced and  
Stratum 4 timing for DS1 interfaces  
Ordering Information  
MT9044AP  
MT9044AL  
MT9044APR  
44 Pin PLCC  
44 Pin MQFP  
44 Pin PLCC  
Tubes  
Trays  
Tape & Reel  
Tape & Reel  
Tubes  
Supports ITU-T G.813 Option 1 clocks for 2048  
kbit/s interfaces  
MT9044APR1 44 Pin PLCC*  
MT9044AP1  
MT9044AL1  
44 Pin PLCC*  
44 Pin MQFP* Trays  
* Pb Free Matte Tin  
-40°C to +85°C  
Supports ITU-T G.812 Type IV clocks for  
1,544 kbit/s interfaces and 2,048 kbit/s interfaces  
Supports ETSI ETS 300 011, TBR 4, TBR 12 and  
TBR 13 timing for E1 interfaces  
Accepts reference inputs from two independent  
sources  
Selectable 1.544 MHz, 2.048 MHz or 8 kHz input  
reference signals  
JTAG Boundary Scan  
Provides C1.5, C2, C3, C4, C6, C8, C16, and C19  
(STS-3/OC3 clock divided by 8) output clock  
signals  
Applications  
Synchronization and timing control for multitrunk  
T1,E1 and STS-3/OC3 systems  
Provides 5 different 8 KHz framing pulses  
Holdover frequency accuracy of 0.05 PPM  
Holdover indication  
ST-BUS clock and frame pulse sources  
Attenuates wander from 1.9 Hz  
Provides Time Interval Error (TIE) correction  
OSCi  
OSCo  
TCLR  
VDD  
VSS  
C19o  
Master Clock  
Virtual  
C1.5o  
TIE  
Reference  
TCK  
C3o  
C2o  
C4o  
C6o  
C8o  
C16o  
F0o  
F8o  
F16o  
RSP  
Corrector  
Circuit  
DPLL  
TDI  
TMS  
TRST  
TDO  
IEEE  
1149.1a  
Output  
Interface  
Circuit  
Selected  
State  
Select  
Reference  
Reference  
Select  
MUX  
PRI  
SEC  
Input  
Impairment  
Monitor  
TIE  
Corrector  
Enable  
State  
Select  
Reference  
Select  
TSP  
Feedback  
RSEL  
LOS1  
LOS2  
Frequency  
Select  
MUX  
Automatic/Manual  
Control State Machine  
Guard Time  
Circuit  
ACKi  
APLL  
ACKo  
MS1  
MS2  
RST HOLDOVER  
GTo  
GTi  
FS1  
FS2  
Figure 1 - Functional Block Diagram  
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,  
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2003 - 2005, Zarlink Semiconductor Inc. All Rights Reserved.  

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