Datasheet > MT9044AL

MT9044AL

更新时间： 2024-01-31 19:57:17

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美高森美 - MICROSEMI		/
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30页	119K
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MT9044AL 数据手册

MT9044

T1/E1/OC3 System Synchronizer

Advance Information

DS5058

ISSUE 3

September 1999

Features

•

Supports AT&T TR62411 and Bellcore

Ordering Information

GR-1244-CORE Stratum 3, Stratum 4

Enhanced and Stratum 4 timing for DS1

interfaces

MT9044AP

MT9044AL

44 Pin PLCC

44 Pin MQFP

•

Supports ITU-T G.812 Type IV clocks for 1,544

kbit/s interfaces and 2,048 kbit/s interfaces

-40 to +85 °C

Description

Supports ETSI ETS 300 011, TBR 4, TBR 12

and TBR 13 timing for E1 interfaces

The MT9044 T1/E1/OC3 System Synchronizer

contains a digital phase-locked loop (DPLL), which

provides timing and synchronization signals for

multitrunk T1 and E1 primary rate transmission links

and STS-3/0C3 links.

Selectable 1.544MHz, 2.048MHz or 8kHz input

reference signals

Provides C1.5, C2, C3, C4, C6, C8, C16, and

C19 (STS-3/OC3 clock divided by 8) output

clock signals

The MT9044 generates ST-BUS clock and framing

signals that are phase locked to either a 2.048MHz,

1.544MHz, or 8kHz input reference.

•

Provides 5 different styles of 8 KHz framing

pulses

•

Holdover frequency accuracy of 0.05 PPM

Holdover indication

The MT9044 is compliant with AT&T TR62411 and

Bellcore GR-1244-CORE Stratum 3, Stratum 4

Enhanced, and Stratum 4; and ETSI ETS 300 011. It

will meet the jitter/wander tolerance, jitter/wander

transfer, intrinsic jitter/wander, frequency accuracy,

capture range, phase change slope, holdover

frequency and MTIE requirements for these

speciﬁcations.

Attenuates wander from 1.9Hz

Provides Time Interval Error (TIE) correction

Accepts reference inputs from two independent

sources

•

JTAG Boundary Scan

Applications

•

Synchronization and timing control for

multitrunk T1,E1 and STS-3/OC3 systems

•

ST-BUS clock and frame pulse sources

OSCi

OSCo

TCLR

VDD

VSS

C19o

Master Clock

Virtual

C1.5o

TIE

Reference

TCK

C3o

C2o

C4o

C6o

C8o

C16o

F0o

F8o

F16o

RSP

Corrector

Circuit

DPLL

TDI

TMS

TRST

TDO

IEEE

1149.1a

Output

Interface

Circuit

Selected

State

Select

Reference

Select

MUX

PRI

SEC

Input

Impairment

Monitor

TIE

Corrector

Enable

State

Select

Reference

Select

TSP

Feedback

Frequency

Select

MUX

RSEL

LOS1

LOS2

Automatic/Manual

Control State Machine

Guard Time

Circuit

ACKi

APLL

ACKo

MS1

MS2

RST HOLDOVER

GTo

GTi

FS1

FS2

Figure 1 - Functional Block Diagram

12 3 4 5 6 7...30

中文翻译

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与MT9044AL相关器件

型号	品牌	获取价格	描述	数据表
MT9044AL1	MICROSEMI	获取价格	Telecom Circuit, 1-Func, PQFP44, 10 X 10 MM, 2 MM HEIGHT, LEAD FREE, MO-112AA-1, MQFP-44
MT9044AL1	ZARLINK	获取价格	Telecom Circuit, 1-Func, CMOS, PQFP44, 10 X 10 MM, 2 MM HEIGHT, LEAD FREE, MO-112AA-1, MQF
MT9044AP	MITEL	获取价格	T1/E1/OC3 System Synchronizer
MT9044AP	ZARLINK	获取价格	Telecom Circuit, 1-Func, CMOS, PQCC44, PLASTIC, MS-018AC, LCC-44
MT9044AP1	MICROSEMI	获取价格	Telecom Circuit, 1-Func, PQCC44, LEAD FREE, PLASTIC, MS-018AC, LCC-44
MT9044APR	MICROSEMI	获取价格	Telecom IC, CMOS, PQCC44
MT9044APR	ZARLINK	获取价格	Telecom Circuit, 1-Func, CMOS, PQCC44, PLASTIC, MS-018AC, LCC-44
MT9044APR1	ZARLINK	获取价格	Telecom Circuit, 1-Func, CMOS, PQCC44, LEAD FREE, PLASTIC, MS-018AC, LCC-44
MT9045	ZARLINK	获取价格	T1/E1/OC3 System Synchronizer
MT9045AN	ZARLINK	获取价格	T1/E1/OC3 System Synchronizer

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