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MT90210 PDF预览

MT90210

更新时间: 2024-02-01 18:17:11
品牌 Logo 应用领域
MITEL /
页数 文件大小 规格书
27页 136K
描述
Multi-Rate Parallel Access Circuit

MT90210 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QFP, QFP100,.7X1.0Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.22
Is Samacsys:NJESD-30 代码:R-PQFP-G100
JESD-609代码:e0长度:20 mm
功能数量:1端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP100,.7X1.0封装形状:RECTANGULAR
封装形式:FLATPACK峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
座面最大高度:3.4 mm子类别:Other Telecom ICs
最大压摆率:0.1 mA标称供电电压:5 V
表面贴装:YES技术:CMOS
电信集成电路类型:TELECOM CIRCUIT温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

MT90210 数据手册

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MT90210  
Multi-Rate Parallel Access Circuit  
Preliminary Information  
DS5026  
ISSUE 2  
August 1998  
Features  
Parallel-to-serial and serial-to-parallel  
Ordering Information  
conversion of up to 1536 full duplex channels or  
3072 time-slots  
MT90210AL  
100 Pin PQFP  
Serial port data rates selectable between 2.048,  
4.096 or 8.192 Mb/s  
-40 to +85°C  
Provides a mechanism for a double buffer  
function to be implemented in external memory  
Description  
24 serial I/O lines programmable in different  
modes: 12 in/12 out at 8.192 Mb/s (1536 full  
duplex channels) or 24 bidirectional line modes  
for 2.048 and 4.096 Mb/s  
The MT90210 is a 100-pin device used to interface a  
parallel bidirectional 8 bit bus to 24 time division  
multiplexed (TDM) serial streams. The device is  
configured to perform simultaneous parallel-to-serial  
and serial-to-parallel conversion with the capability  
of handling up to 3072 channels, 1536 on the  
transmit and 1536 on the receive direction.  
Depending on the operation mode selected at the  
mode pins, the individual 64 Kb/s channels on the  
serial links may be configured as inputs or outputs.  
The data on the parallel bus is in a format suitable for  
interfacing with a dual-port RAM. Depending on the  
data rate selected by the MD0-MD2 input pins, serial  
data is clocked in and out on the serial streams at  
either 2.048, 4.096 or 8.192 Mb/s.  
Provides a bidirectional 8-bit parallel port  
operating at 16.384 or 32.768 MByte/s for direct  
interface to external memory (dual port)  
Provides an external 13-bit output address bus  
for direct connection with an 8K-position dual  
port memory  
JTAG boundary scan  
Applications  
Fast access to ST-BUS, SCSA, MVIP, and  
H-MVIP serial backplanes  
Voice processing cards for Computer Telephony  
Integration (CTI)  
Video and teleconferencing bridge cards  
Fast DSP access to serial TDM buses  
RDin Strobe RBC R/W1 R/W2  
P0  
External Memory  
Access Control  
P7  
WBC  
S0  
SCLK  
HC4  
Shift  
Registers  
C16-  
C16+  
F0i  
Timing  
Generation  
PCLK  
PLLVSS  
LP1,LP2  
PLLAGND  
CKout  
RST  
Generator  
Address  
Read  
Counter  
Analog  
PLL  
Write  
Counter  
Boundary  
Scan Test  
S23  
PLLVDD  
MUX  
Mode Control  
OEser MD2 MD1 MD0  
Figure 1 - Functional Block Diagram  
2-145  

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