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MT8981DE PDF预览

MT8981DE

更新时间: 2024-11-17 22:51:03
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 开关电信集成电路光电二极管
页数 文件大小 规格书
17页 564K
描述
Digital Switch

MT8981DE 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:DIP, DIP40,.6Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.58
JESD-30 代码:R-PDIP-T40JESD-609代码:e0
长度:51.75 mm功能数量:1
端子数量:40最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP40,.6
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):225电源:5 V
认证状态:Not Qualified座面最大高度:6.35 mm
子类别:Other Telecom ICs最大压摆率:0.01 mA
标称供电电压:5 V表面贴装:NO
技术:CMOS电信集成电路类型:DIGITAL TIME SWITCH
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:15.24 mmBase Number Matches:1

MT8981DE 数据手册

 浏览型号MT8981DE的Datasheet PDF文件第2页浏览型号MT8981DE的Datasheet PDF文件第3页浏览型号MT8981DE的Datasheet PDF文件第4页浏览型号MT8981DE的Datasheet PDF文件第5页浏览型号MT8981DE的Datasheet PDF文件第6页浏览型号MT8981DE的Datasheet PDF文件第7页 
ISO-CMOS ST-BUSFAMILY MT8981D  
Digital Switch  
ISSUE8  
March 1997  
Features  
Ordering Information  
Zarlink ST-BUS compatible  
MT8981DE  
MT8981DP  
40 Pin Plastic DIP  
44 PLCC  
4-line x 32-channel inputs  
4-line x 32-channel outputs  
128 ports non-blocking switch  
Single power supply (+5 V)  
Low power consumption: 30 mW Typ.  
Microprocessor-control interface  
Three-state serial outputs  
-40°C to +85°C  
Description  
This VLSI ISO-CMOS device is designed for  
switching PCM-encoded voice or  
microprocessor control, in  
data, under  
modern digital  
a
exchange, PBX or Central Office. It provides  
simultaneous connections for up to 128 64 kbit/s  
channels. Each of the four serial inputs and outputs  
consist of 32 64 kbit/s channels multiplexed to form a  
2048 kbit/s ST-BUS stream. In addition, the MT8981  
provides microprocessor read and write access to  
individual ST-BUS channels.  
V
V
ODE  
DD  
SS  
F0i  
C4i  
Frame  
Counter  
Output  
MUX  
STo0  
STo1  
STo2  
STo3  
STi0  
Parallel  
to  
Serial  
to  
Data  
STi1  
STi2  
STi3  
Memory  
Serial  
Parallel  
Converter  
Control Register  
Control Interface  
Converter  
Connection  
Memory  
DS CS R/W A5/ DTA D7/  
A0 D0  
Figure 1 - Functional Block Diagram  
2-17  

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