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MT88L70ASR1 PDF预览

MT88L70ASR1

更新时间: 2024-02-12 13:04:15
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 电信集成电路电信信令电路电信电路光电二极管
页数 文件大小 规格书
16页 476K
描述
3 Volt Integrated DTMF Receiver

MT88L70ASR1 技术参数

是否Rohs认证:符合生命周期:Transferred
包装说明:SOP, SOP18,.4Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.63
Is Samacsys:NJESD-30 代码:R-PDSO-G18
JESD-609代码:e3长度:11.55 mm
湿度敏感等级:3功能数量:1
端子数量:18最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP18,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:3 V
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Telecom Signaling Circuits最大压摆率:0.0055 mA
标称供电电压:3 V表面贴装:YES
电信集成电路类型:DTMF SIGNALING CIRCUIT温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
Base Number Matches:1

MT88L70ASR1 数据手册

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MT88L70  
3 Volt Integrated DTMF Receiver  
Data Sheet  
August 2005  
Features  
2.7 - 3.6 volt operation  
Ordering Information  
Complete DTMF receiver  
Low power consumption  
Internal gain setting amplifier  
Adjustable guard time  
MT88L70AE  
18 Pin PDIP  
18 Pin SOIC  
Tubes  
Tubes  
MT88L70AS  
MT88L70AN  
MT88L70ASR  
MT88L70ANR  
MT88L70AE1  
MT88L70AN1  
MT88L70ANR1  
MT88L70AS1  
MT88L70ASR1  
20 Pin SSOP Tubes  
18 Pin SOIC  
Tape & Reel  
20 Pin SSOP Tape & Reel  
18 Pin PDIP* Tubes  
20 Pin SSOP* Tubes  
20 Pin SSOP* Tape & Reel  
18 Pin SOIC* Tubes  
18 Pin SOIC* Tape & Reel  
Central office quality  
Power-down mode  
Inhibit mode  
* Pb Free Matte Tin  
-40°C to +85°C  
Functionally compatible with Zarlink’s MT8870D  
Description  
Applications  
The MT88L70 is a complete 3 Volt, DTMF receiver  
integrating both the bandsplit filter and digital decoder  
functions. The filter section uses switched capacitor  
techniques for high and low group filters; the decoder  
uses digital counting techniques to detect and decode  
all 16 DTMF tone-pairs into a 4-bit code. External  
component count is minimized by on chip provision of  
a differential input amplifier, clock oscillator and latched  
three-state bus interface.  
Paging systems  
Repeater systems/mobile radio  
Credit card systems  
Remote control  
Personal computers  
Telephone answering machine  
VDD  
VSS  
VRef  
INH  
Bias  
Circuit  
PWDN  
IN +  
VRef  
Buffer  
Q1  
Chip Chip  
Power Bias  
High Group  
Filter  
Digital  
Code  
Detection  
Algorithm  
Converter  
and Latch  
Q2  
Q3  
Q4  
Dial  
Tone  
Filter  
Zero Crossing  
Detectors  
IN -  
GS  
Low Group  
Filter  
to all  
St  
GT  
Steering  
Logic  
Chip  
Clocks  
OSC1  
OSC2  
St/GT  
ESt  
STD  
TOE  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved.  

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