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MT88E43BE PDF预览

MT88E43BE

更新时间: 2024-01-08 06:49:30
品牌 Logo 应用领域
加拿大卓联 - ZARLINK /
页数 文件大小 规格书
29页 560K
描述
Extended Voltage Calling Number Identification Circuit 2

MT88E43BE 数据手册

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CMOS MT88E43B  
Extended Voltage Calling Number  
Identification Circuit 2  
Data Sheet  
April 2006  
Features  
Compatible with:  
Ordering Information  
British Telecom (BT) SIN227 & SIN242  
MT88E43BE  
MT88E43BS  
24 Pin PDIP  
24 Pin SOIC  
Tubes  
U.K.’s Cable Communications Association  
Tubes  
(CCA) specification TW/P&E/312  
MT88E43BSR 24 Pin SOIC  
Tape & Reel  
MT88E43BS1 24 Pin SOIC* Tubes  
Bellcore GR-30-CORE (formerly known as  
TR-NWT-000030) & SR-TSV-002476  
MT88E43BSR1 24 Pin SOIC* Tape & Reel  
*Pb Free Matte Tin  
Bellcore "CPE Alerting Signal (CAS)" and BT  
-40°C to +85°C  
"Idle State Tone Alert Signal" detection  
Feature phones, including Analog Display  
Ring and line reversal detection  
Services Interface (ADSI) phones  
1200 baud Bell 202 and CCITT V.23 Frequency  
Phone set adjunct boxes  
Shift Keying (FSK) demodulation  
FAX and answering machines  
3 or 5 V ±10% supply voltage  
Database query and Computer Telephony  
High input sensitivity (-40 dBV Tone and FSK  
Integration (CTI) systems  
Detection)  
Selectable 3-wire data interface (microcontroller  
or MT88E43 controlled)  
Description  
The MT88E43 Calling Number Identification Circuit 2  
(ECNIC2) is a low power CMOS integrated circuit  
intended for receiving physical layer signals  
transmitted according to BT (British Telecom) SIN227  
& SIN242, the U.K.’s CCA (Cable Communications  
Association) TW/P&E/312 and Bellcore GR-30-CORE  
& SR-TSV-002476 specifications. The MT88E43 is  
suitable for applications using a fixed voltage power  
source between 3 and 5 V ±10%.  
Low power CMOS with powerdown mode  
Input gain adjustable amplifier  
Carrier detect status output  
Uses 3.58 MHz crystal  
Applications  
BT Calling Line Identity Presentation (CLIP), CCA  
CLIP, and Bellcore Calling Identity Delivery (CID)  
systems  
MODE  
FSKen  
IN+  
DCLK  
DATA  
DR  
+
FSK  
Anti-alias  
Data Timing  
Recovery  
FSK Bandpass  
Filter  
-
Demodulator  
IN-  
Filter  
GS  
To internal  
cct.  
CD  
Carrier  
Bias  
Detector  
VRef  
Generator  
Interrupt  
INT  
Generator  
CAP  
PWDN  
Alert Signal High  
Tone Filter  
StD  
Guard  
Time  
Tone  
St/GT  
Detection  
Algorithm  
To internal cct.  
Alert Signal Low  
Tone Filter  
ESt  
Oscillator  
VDD  
VSS  
OSCin OSCout TRIGin  
TRIGRC  
TRIGout  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 1997-2006, Zarlink Semiconductor Inc. All Rights Reserved.  

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