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MT8885AP

更新时间： 2024-02-01 10:53:45
品牌 Logo 应用领域
MITEL 电信集成电路
页数 文件大小 规格书
20页 353K
描述
Integrated DTMFTransceiver with Power Down & Adaptive Micro Interface

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中文翻译

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MT8885AP 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：DIP, DIP24,.6Reach Compliance Code：unknown
风险等级：5.85JESD-30 代码：R-PDIP-T24
JESD-609代码：e0端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP24,.6封装形状：RECTANGULAR
封装形式：IN-LINE电源：5 V
认证状态：Not Qualified子类别：Telecom Signaling Circuits
最大压摆率：11 mA标称供电电压：5 V
表面贴装：NO技术：CMOS
电信集成电路类型：DTMF SIGNALING CIRCUIT温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
Base Number Matches：1

MT8885AP 数据手册

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MT8885  
Integrated DTMF Transceiver  
with Power Down & Adaptive  
Micro Interface  
Advance Information  
ISSUE 1  
May 1995  
Features  
•
External power down pin  
Ordering Information  
MT8885AE 24 Pin Plastic DIP  
•
Central office quality DTMF transmitter/  
receiver  
MT8885AN  
MT8885AP  
24 Pin SSOP  
28 Pin PLCC  
•
•
•
•
•
•
Low power consumption  
High speed adaptive micro interface  
Adjustable guard time  
-40°C to +85°C  
Automatic tone burst mode  
The receiver section is based upon the industry  
standard MT8870 DTMF receiver while the  
Call progress tone detection to -30dBm  
DTMF transmitter/receiver power down via  
register control  
transmitter utilizes  
a
switched capacitor D/A  
converter for low distortion, high accuracy DTMF  
signalling. Internal counters provide a burst mode  
such that tone bursts can be transmitted with precise  
timing. A call progress filter can be selected allowing  
a microprocessor to analyze call progress tones.  
Applications  
•
•
•
•
•
Credit card systems  
Paging systems  
Repeater systems/mobile radio  
Interconnect dialers  
Personal computers  
The MT8885 utilizes an adaptive micro interface,  
which allows the device to be connected to a number  
of popular microcontrollers with minimal external  
logic. The MT8885 provides enhanced power down  
features.  
The transmitter and receiver may  
Description  
The MT8885 is a monolithic DTMF transceiver with  
call progress filter.  
technology offering low power consumption and high  
reliability.  
independently be powered down via register  
control. A full chip power down pin provides simple  
power and control capability.  
It is fabricated in CMOS  
D0  
Data  
Row and  
D/A  
Transmit Data  
Bus  
D1  
D2  
D3  
∑
Column  
TONE  
Converters  
Register  
Buffer  
Counters  
Status  
Register  
Interrupt  
Logic  
Tone Burst  
Gating Cct.  
Control  
Logic  
IRQ/CP  
Control  
Register  
A
IN+  
IN-  
GS  
+
-
Dial  
Tone  
Filter  
High Group  
Filter  
Digital  
DS/RD  
CS  
Algorithm  
and Code  
Converter  
Control  
Register  
B
I/O  
Low Group  
Filter  
Control  
OSC1  
OSC2  
Oscillator  
Circuit  
R/W/WR  
RS0  
Control  
Logic  
Receive Data  
Register  
Steering  
Logic  
Bias  
Circuit  
VDD VRef VSS  
ESt  
St/GT  
PWDN  
Figure 1 - Functional Block Diagram  
4-51  
1234567...20

中文翻译

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