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MT8880CE/CE-1 PDF预览

MT8880CE/CE-1

更新时间: 2024-02-22 00:46:43
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MITEL /
页数 文件大小 规格书
18页 315K
描述
Integrated DTMFTransceiver

MT8880CE/CE-1 数据手册

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ISO2-CMOS  
MT8880C/MT8880C-1  
Integrated DTMF Transceiver  
ISSUE 2  
May 1995  
Features  
Ordering Information  
Complete DTMF transmitter/receiver  
MT8880CE/CE-1  
20 Pin Plastic DIP  
20 Pin Ceramic DIP  
20 Pin SOIC  
24 Pin SSOP  
28 Pin Plastic LCC  
MT8880CC/CC-1  
MT8880CS/CS-1  
MT8880CN/CN-1  
MT8880CP/CP-1  
Central office quality  
Low power consumption  
Microprocessor port  
Adjustable guard time  
Automatic tone burst mode  
Call progress mode  
-40°C to +85°C  
based upon the industry standard MT8870  
monolithic DTMF receiver; the transmitter utilizes a  
switched capacitor D/A converter for low distortion,  
high accuracy DTMF signalling. Internal counters  
provide a burst mode such that tone bursts can be  
transmitted with precise timing. A call progress filter  
can be selected allowing a microprocessor to  
Applications  
Credit card systems  
Paging systems  
analyze  
call  
progress  
tones.  
A
standard  
Repeater systems/mobile radio  
Interconnect dialers  
Personal computers  
microprocessor bus is provided and is directly  
compatible with 6800 series microprocessors. The  
MT8880C-1 is functionally identical to the MT8880C  
except for the performance of the receiver section,  
which is enhanced to accept and reject lower signal  
levels.  
Description  
The MT8880C/C-1 is a monolithic DTMF transceiver  
with call progress filter. It is fabricated in Mitel’s  
2
ISO -CMOS technology, which provides low power  
dissipation and high reliability. The DTMF receiver is  
D0  
Data  
Bus  
Buffer  
Row and  
D/A  
Transmit Data  
D1  
D2  
D3  
Column  
TONE  
Converters  
Register  
Counters  
Status  
Register  
Interrupt  
Logic  
Tone Burst  
Gating Cct.  
Control  
Logic  
IRQ/CP  
Control  
Register  
A
IN+  
IN-  
GS  
+
-
Dial  
Tone  
Filter  
High Group  
Filter  
Digital  
Φ2  
Algorithm  
and Code  
Converter  
Control  
Register  
B
I/O  
Control  
CS  
Low Group  
Filter  
OSC1  
OSC2  
Oscillator  
R/W  
RS0  
Circuit  
Control  
Logic  
Receive Data  
Register  
Steering  
Logic  
Bias  
Circuit  
VDD VRef VSS  
ESt  
St/GT  
Figure 1 - Functional Block Diagram  
4-33  

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