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MT8812AP PDF预览

MT8812AP

更新时间: 2024-01-19 22:52:20
品牌 Logo 应用领域
加拿大卓联 - ZARLINK PC输出元件
页数 文件大小 规格书
9页 483K
描述
Cross Point Switch, 1 Func, 12 Channel, CMOS, PQCC44, PLASTIC, MS-018AC, LCC-44

MT8812AP 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QCCJ, LDCC44,.7SQReach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.21
Is Samacsys:N其他特性:8 X 12 ARRAY
模拟集成电路 - 其他类型:CROSS POINT SWITCHJESD-30 代码:S-PQCC-J44
JESD-609代码:e0长度:16.585 mm
湿度敏感等级:1信道数量:12
功能数量:1端子数量:44
标称断态隔离度:95 dB通态电阻匹配规范:5 Ω
最大通态电阻 (Ron):220 Ω最高工作温度:70 °C
最低工作温度:输出:SEPARATE OUTPUT
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC44,.7SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):225
电源:5/14,GND/-7 V认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Multiplexer or Switches
最大供电电压 (Vsup):14.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
最长接通时间:100 ns技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:16.585 mmBase Number Matches:1

MT8812AP 数据手册

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ISO-CMOS MT8812  
8 x 12 Analog Switch Array  
ISSUE 6  
March 1997  
Features  
Ordering Information  
Internal control latches and address decoder  
MT8812AE  
MT8812AP  
40 Pin Plastic DIP  
44 Pin PLCC  
Short set-up and hold times  
Wide operating voltage: 4.5V to 14.5V  
14Vpp analog signal capability  
0° to 70°C  
R
65max. @ V =14V, 25°C  
ON  
DD  
R  
10@ V =14V, 25°C  
ON  
DD  
Description  
Full CMOS switch for low distortion  
Minimum feedthrough and crosstalk  
The Zarlink MT8812 is fabricated in Zarlink’s ISO-  
CMOS technology providing low power dissipation  
and high reliability. The device contains a 8 x12 array  
of crosspoint switches along with a 7 to 96 line  
decoder and latch circuits. Any one of the 96  
switches can be addressed by selecting the  
appropriate seven input bits. The selected switch can  
be turned on or off by applying a logical one or zero  
to the DATA input.  
Low power consumption ISO-CMOS technology  
Applications  
PBX systems  
Mobile radio  
Test equipment /instrumentation  
Analog/digital multiplexers  
Audio/Video switching  
STROBE  
DATA RESET  
VDD  
VSS  
1
1
AX0  
AX1  
AX2  
AX3  
AY0  
AY1  
AY2  
8 x 12  
Switch  
Array  
7 to 96  
Decoder  
Xi I/O  
(i=0-11)  
Latches  
96  
96  
• • • • • • • • • • • • • • • • • • •  
Yi I/O (i=0-7)  
Figure 1 - Functional Block Diagram  
3-27  

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