SRAM
MT5C1009
128K x 8 SRAM
WITH CHIP & OUTPUT ENABLE
PIN ASSIGNMENT
(Top View)
32-Pin DIP (C, CW)
32-Pin SOJ (SOJ)
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
AVAILABLE AS MILITARY
SPECIFICATIONS
•SMD 5962-89598
•MIL-STD-883
VCC
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2 10
A1 11
A0 12
DQ1 13
DQ2 14
DQ3 15
1
2
3
4
5
6
7
8
9
32
VCC
A15
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
VSS
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
31 A15
NC
30 CE2
NC
CE2
29 WE\
28 A13
27 A8
WE\
A13
A8
FEATURES
• Access Times: 12, 15, 20, 25, 35, 45, 55 and 70 ns
• Battery Backup: 2V data retention
• Low power standby
• High-performance, low-power CMOS process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\ and OE\ options.
• All inputs and outputs are TTL compatible
A9
26 A9
A11
OE\
A10
CE\
DQ8
DQ7
DQ6
DQ5
DQ4
25 A11
24 OE\
23 A10
22 CE\
21 DQ8
20 DQ7
19 DQ6
18 DQ5
17 DQ4
9
10
11
12
13
14
15
16
VSS
16
32-Pin LCC (ECA)
32-Pin Flat Pack (F)
4
3 2 1 32 31 30
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2 10
A1 11
A0 12
DQ1 13
DQ2 14
DQ3 15
VSS 16
1
2
3
4
5
6
7
8
9
32 VCC
31 A15
OPTIONS
• Timing
MARKING
NC
30 CE2
5
6
7
8
9
10
11
12
13
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
29
28
27
26
25
24
23
22
21
\
WE
29 WE\
28 A13
27 A8
A13
A8
26 A9
A9
25 A11
24 OE\
23 A10
22 CE\
21 DQ8
20 DQ7
19 DQ6
18 DQ5
17 DQ4
A11
\
12ns access
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
-12 (IT only)
-15
-20
-25
-35
-45
-55*
-70*
OE
A10
CE1
\
DQ8
14 15 16 17 18 19 20
GENERAL DESCRIPTION
The MT5C1009 is a 1,048,576-bit high-speed CMOS
static RAM organized as 131,072 words by 8 bits. This device
uses 8 common input and output lines and has an output en-
able pin which operate faster than address access times during
READ cycle.
For design flexibility in high-speed memory applica-
tions, this device offers chip enable (CE\) and output enable
(OE\) features. These enhancements can place the outputs in
High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is ac-
complished when WE\ remains HIGH and CE\ and OE\ go
LOW. The devices offer a reduced power standby mode when
disabled, allowing system designs to achieve low standby power
requirements.
• Package(s)•
Ceramic DIP (400 mil)
Ceramic DIP (600 mil)
Ceramic LCC
Ceramic LCC
Ceramic Flatpack
Ceramic SOJ
C
No. 111
CW
EC
ECA
F
DCJ
SOJ
No. 112
No. 207
No. 208
No. 303
No. 501
No. 507
Ceramic SOJ
• 2V data retention/low power
L
*Electrical characteristics identical to those provided for the 45ns
access devices.
The “L” version offers a 2V data retention mode,
reducing current consumption to 2mW maximum.
All devices operate from a single +5V power supply
and all inputs and outputs are fully TTL compatible. It is par-
ticularly well suited for use in high-density, high-speed system
applications.
For more products and information
please visit our web site at
www.micross.com
Micross Components reserves the right to change products or specifications without notice.
MT5C1009
Rev. 6.2 01/10
1