2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
2Mb SYNCBURST™
SRAM
MT58L128L18P, MT58L64L32P, MT58L64L36P;
MT58L128V18P, MT58L64V32P, MT58L64V36P
3.3V VDD, 3.3V or 2.5V I/O, Pipelined, Single-
Cycle Deselect
FEATURES
• Fast clock and OE# access times
• Single +3.3V +0.3V/-0.165V power supply (VDD)
• Separate +3.3V or +2.5V isolated output buffer
supply (VDDQ)
100-PinTQFP**
• SNOOZE MODE for reduced-power standby
• Single-cycle deselect (Pentium® BSRAM-compatible)
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL
WRITE
• Three chip enables for simple depth expansion
and address pipelining
• Clock-controlled and registered addresses, data
I/Os and control signals
• Internally self-timed WRITE cycle
• Burst control pin (interleaved or linear burst)
• Automatic power-down for portable applications
• 100-pin TQFP package
**JEDEC-standard MS-026 BHA (LQFP).
• Low capacitive bus loading
• x18, x32, and x36 options available
GENERALDESCRIPTION
The Micron® SyncBurst™ SRAM family employs
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
OPTIONS
MARKING
• Timing (Access/Cycle/MHz)
3.5ns/5ns/200 MHz
3.5ns/6ns/166 MHz
4.0ns/7.5ns/133 MHz
5ns/10ns/100 MHz
-5
-6
-7.5
-10
Micron’s 2Mb SyncBurst SRAMs integrate a 128K x
18, 64K x 32, or 64K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single clock
input (CLK). The synchronous inputs include all
addresses,alldatainputs,activeLOWchipenable(CE#),
two additional chip enables for easy depth expansion
(CE2, CE2#), burst control inputs (ADSC#, ADSP#,
ADV#), byte write enables (BWx#), and global write
(GW#).
Asynchronous inputs include the output enable
(OE#), clock (CLK), and snooze enable (ZZ). There is
also a burst mode pin (MODE) that selects between
interleaved and linear burst modes. The data-out (Q),
enabled by OE#, is also asynchronous. WRITE cycles
can be from one to two bytes wide (x18) or from one
to four bytes wide (x32/x36), as controlled by the write
control inputs.
• Configurations
3.3V I/O
128K x 18
64K x 32
64K x 36
MT58L128L18P
MT58L64L32P
MT58L64L36P
2.5V I/O
128K x 18
64K x 32
64K x 36
MT58L128V18P
MT58L64V32P
MT58L64V36P
• Package
100-pin TQFP
T
• Operating Temperature Range
Commercial (0°C to +70°C)
None
Part Number Example:
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) input pins. Subsequent burst addresses can be
internally generated as controlled by the burst advance
pin (ADV#).
MT58L128L18PT-10
2Mb:128Kx18, 64Kx32/36Pipelined, SCDSyncBurstSRAM
MT58L128L18P_2.p65 – Rev. 6/01
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
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©2000,MicronTechnology,Inc.