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MT58L64L36FT-10T PDF预览

MT58L64L36FT-10T

更新时间: 2024-11-08 07:12:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
17页 243K
描述
Cache SRAM, 64KX36, 10ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100

MT58L64L36FT-10T 数据手册

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2Mb: 128K x 18, 64K x 32/36  
FLOW-THROUGH SYNCBURST SRAM  
MT58L128L18F, MT58L64L32F,  
MT58L64L36F; MT58L128V18F,  
MT58L64V32F, MT58L64V36F  
2Mb SYNCBURST™  
SRAM  
3.3V VDD, 3.3V or 2.5V I/O, Flow-Through  
FEATURES  
• Fast clock and OE# access times  
100-Pin TQFP**  
• Single +3.3V +0.3V/ -0.165V power supply (VDD)  
• Separate +3.3V or +2.5V isolated output buffer supply  
(VDDQ)  
(D-1)  
• SNOOZE MODE for reduced-power standby  
• Common data inputs and data outputs  
• Individual BYTE WRITE control and GLOBAL WRITE  
• Three chip enables for simple depth expansion and  
address pipelining  
• Clock-controlled and registered addresses, data I/ Os  
and control signals  
• Internally self-timed WRITE cycle  
• Burst control pin (interleaved or linear burst)  
• Automatic power-down for portable applications  
• 100-lead TQFP package for high density, high speed  
• Low capacitive bus loading  
• x18, x32 and x36 versions available  
**JEDEC-standard MS-026 BHA (LQFP).  
OPTIONS  
MARKING  
• Timing (Access/ Cycle/ MHz)  
6.8ns/ 8.0ns/ 125 MHz  
7.5ns/ 8.8ns/ 113 MHz  
8.5ns/ 10ns/ 100 MHz  
10ns/ 15ns/ 66 MHz  
-6.8  
-7.5  
-8.5  
-10  
GENERAL DESCRIPTION  
®
The Micron SyncBurst SRAM family employs high-  
speed, low-power CMOS designs that are fabricated using  
an advanced CMOS process.  
Microns 2Mb SyncBurst SRAMs integrate a 128K x 18,  
64Kx32,or 64Kx36SRAM corewith advanced synchronous  
peripheral circuitry and a 2-bit burst counter. All  
synchronous inputs pass through registers controlled by a  
positive-edge-triggered single clock input (CLK). The  
synchronous inputs include all addresses, all data inputs,  
active LOW chip enable (CE#), two additional chip enables  
for easy depth expansion (CE2, CE2#), burst control inputs  
(ADSC#, ADSP#, ADV#), byte write enables (BWx#) and  
global write (GW#).  
• Configurations  
3.3V I/ O  
128K x 18  
64K x 32  
64K x 36  
MT58L128L18F  
MT58L64L32F  
MT58L64L36F  
2.5V I/ O  
128K x 18  
64K x 32  
64K x 36  
MT58L128V18F  
MT58L64V32F  
MT58L64V36F  
Asynchronous inputs include the output enable (OE#),  
snooze enable (ZZ) and clock (CLK). There is also a burst  
mode pin (MODE) that selects between interleaved and  
linear burst modes. The data-out (Q), enabled by OE#, is  
also asynchronous. WRITE cycles can be from one to two  
bytes wide (x18) or from one to four bytes wide (x32/ x36),  
as controlled by the write control inputs.  
• Package  
100-pin TQFP  
T
• Temperature  
Commercial (0°C to +70°C)  
Industrial (-40°C to +85°C)  
None  
T*  
Burst operation can be initiated with either address status  
processor (ADSP#) or address status controller (ADSC#)  
input pins. Subsequent burst addresses can be internally  
generated as controlled by the burst advance pin (ADV#).  
• Part Number Example: MT58L64L36FT-8.5 T  
*Under consideration.  
2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM  
MT58L128L18F.p65 – Rev. 6/99  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
1999, Micron Technology, Inc.  
All registered and unregistered trademarks are the sole property of their respective companies.  
1

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