Datasheet > MT58L64L36DT-6

MT58L64L36DT-6

更新时间： 2024-11-08 04:27:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
19页	414K
描述
Cache SRAM, 64KX36, 3.5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

MT58L64L36DT-6 数据手册

2Mb: 128K x 18, 64K x 32/36

PIPELINED, DCD SYNCBURST SRAM

2Mb SYNCBURST^™

SRAM

MT58L128L18D, MT58L64L32D,

MT58L64L36D

3.3V VDD, 3.3V I/O, Pipelined, Double-Cycle

Deselect

FEATURES

• Fast clock and OE# access times

• Single +3.3V +0.3V/-0.165V power supply (V^DD)

• Separate +3.3V isolated output buffer supply

(VDDQ)

100-PinTQFP**

• SNOOZE MODE for reduced-power standby

• Common data inputs and data outputs

• Individual BYTE WRITE control and GLOBAL

WRITE

• Three chip enables for simple depth expansion and

address pipelining

• Clock-controlled and registered addresses, data

I/Os and control signals

• Internally self-timed WRITE cycle

• Burst control pin (interleaved or linear burst)

• Automatic power-down

**JEDEC-standard MS-026 BHA (LQFP).

• 100-pin TQFP package

• Low capacitive bus loading

• x18, x32, and x36 options available

controlled by a positive-edge-triggered single clock

input (CLK). The synchronous inputs include all ad-

dresses, all data inputs, active LOW chip enable (CE#),

two additional chip enables for easy depth expansion

(CE2, CE2#), burst control inputs (ADSC#, ADSP#,

ADV#), byte write enables (BWx#) and global write

(GW#).

Asynchronous inputs include the output enable

(OE#), clock (CLK) and snooze enable (ZZ). There is also

a burst mode pin (MODE) that selects between inter-

leaved and linear burst modes. The data-out (Q), en-

abled by OE#, is also asynchronous. WRITE cycles can

be from one to two bytes wide (x18) or from one to four

bytes wide (x32/x36), as controlled by the write control

inputs.

OPTIONS

MARKING*

• Timing (Access/Cycle/MHz)

3.5ns/6ns/166 MHz

4.0ns/7.5ns/133 MHz

5ns/10ns/100 MHz

-6

-7.5

-10

• Configurations

128K x 18

MT58L128L18D

MT58L64L32D

MT58L64L36D

64K x 32

64K x 36

• Packages

100-pin TQFP

• Operating Temperature Range

Commercial (0°C to +70°C)

None

Burst operation can be initiated with either address

status processor (ADSP#) or address status controller

(ADSC#) input pins. Subsequent burst addresses can be

internally generated as controlled by the burst advance

pin (ADV#).

Address and write control are registered on-chip to

simplify WRITE cycles. This allows self-timed WRITE

cycles. Individual byte enables allow individual bytes

to be written. During WRITE cycles on the x18 device,

BWa# controls DQa pins and DQPa; BWb# controls

DQb pins and DQPb. During WRITE cycles on the x32

and x36 devices, BWa# controls DQa pins and DQPa;

BWb# controls DQb pins and DQPb; BWc# controls

Part Number Example:

MT58L128L18DT-10

GENERALDESCRIPTION

The Micron^®SyncBurst^™SRAM family employs

high- speed, low-power CMOS designs that are fabri-

cated using an advanced CMOS process.

Micron’s 2Mb SyncBurst SRAMs integrate a 128K x

18, 64K x 32, or 64K x 36 SRAM core with advanced

synchronous peripheral circuitry and a 2-bit burst

counter. All synchronous inputs pass through registers

2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM

MT58L128L18D_2.p65 – Rev. 6/01

Micron Technology, Inc., reserves the right to change products or specifications without notice.

12 3 4 5 6 7...19

中文翻译

下载PDF

与MT58L64L36DT-6相关器件

型号	品牌	获取价格	描述	数据表
MT58L64L36DT-6IT	CYPRESS	获取价格	Cache SRAM, 64KX36, 3.5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L64L36DT-6T	CYPRESS	获取价格	Standard SRAM, 64KX36, 3.5ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100
MT58L64L36DT-7.5	CYPRESS	获取价格	Cache SRAM, 64KX36, 4ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L64L36DT-7.5IT	CYPRESS	获取价格	Cache SRAM, 64KX36, 4ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L64L36F	MICRON	获取价格	2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM
MT58L64L36FF-7.5	CYPRESS	获取价格	Standard SRAM, 64KX36, 7.5ns, CMOS, PBGA165, FBGA-165
MT58L64L36FF8.5	CYPRESS	获取价格	64KX36 STANDARD SRAM, 8.5ns, PBGA165, FBGA-165
MT58L64L36FF-8.5	CYPRESS	获取价格	64KX36 STANDARD SRAM, 8.5ns, PBGA165, FBGA-165
MT58L64L36FT-10	MICRON	获取价格	2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM
MT58L64L36FT-10T	CYPRESS	获取价格	Cache SRAM, 64KX36, 10ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100

与MT58L64L36DT-6相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

18
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

15
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

38
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

36

产品中心

服务支持

精选活动

关于我们

帮助中心

MT58L64L36DT-6

MT58L64L36DT-6 数据手册

与MT58L64L36DT-6相关器件

与MT58L64L36DT-6相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MT58L64L36DT-6

MT58L64L36DT-6 数据手册

与MT58L64L36DT-6相关器件

与MT58L64L36DT-6相关文章

您还可以找

您在本页遇到什么问题？