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MT58L512L18PT-6 PDF预览

MT58L512L18PT-6

更新时间: 2024-02-27 22:38:42
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
27页 393K
描述
Cache SRAM, 512KX18, 3.5ns, CMOS, PQFP100, PLASTIC, TQFP-100

MT58L512L18PT-6 技术参数

生命周期:Transferred零件包装代码:QFP
包装说明:LQFP,针数:100
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.39
Is Samacsys:N最长访问时间:3.5 ns
其他特性:AUTOMATIC POWER DOWN; SELF-TIMED WRITE CYCLE; INDIVIDUAL BYTE WRITEJESD-30 代码:R-PQFP-G100
长度:20 mm内存密度:9437184 bit
内存集成电路类型:CACHE SRAM内存宽度:18
功能数量:1端子数量:100
字数:524288 words字数代码:512000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:512KX18
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
宽度:14 mmBase Number Matches:1

MT58L512L18PT-6 数据手册

 浏览型号MT58L512L18PT-6的Datasheet PDF文件第2页浏览型号MT58L512L18PT-6的Datasheet PDF文件第3页浏览型号MT58L512L18PT-6的Datasheet PDF文件第4页浏览型号MT58L512L18PT-6的Datasheet PDF文件第5页浏览型号MT58L512L18PT-6的Datasheet PDF文件第6页浏览型号MT58L512L18PT-6的Datasheet PDF文件第7页 
8Mb: 512K x 18, 256K x 32/36  
PIPELINED, SCD SYNCBURST SRAM  
8Mb SYNCBURST™  
SRAM  
MT58L512L18P, MT58L256L32P, MT58L256L36P;  
MT58L512V18P, MT58L256V32P, MT58L256V36P  
3.3V VDD, 3.3V or 2.5V I/O, Pipelined, Single-Cycle  
Deselect  
FEATURES  
1
100-Pin TQFP  
• Fast clock and OE# access times  
• Single +3.3V +0.3V/-0.165V power supply (VDD)  
• Separate +3.3V or +2.5V isolated output buffer  
supply (VDDQ)  
• SNOOZE MODE for reduced-power standby  
• Single-cycle deselect (Pentium® BSRAM-compatible)  
• Common data inputs and data outputs  
• Individual BYTE WRITE control and GLOBAL  
WRITE  
• Three chip enables for simple depth expansion  
and address pipelining  
• Clock-controlled and registered addresses, data  
I/Os and control signals  
165-Pin FBGA  
• Internally self-timed WRITE cycle  
• Burst control (interleaved or linear burst)  
• Automatic power-down for portable applications  
• 100-pin TQFP package  
• 165-pin FBGA package  
• Low capacitive bus loading  
• x18, x32, and x36 versions available  
OPTIONS  
MARKING  
• Timing (Access/Cycle/MHz)  
3.5ns/6ns/166 MHz  
4.0ns/7.5ns/133 MHz  
5ns/10ns/100 MHz  
• Configurations  
3.3V I/O  
-6  
-7.5  
-10  
NOTE:1. JEDEC-standard MS-026 BHA (LQFP).  
* A Part Marking Guide for the FBGA devices can be found on Micron’s  
Web site—http://www.micron.com/support/index.html.  
**Industrial temperature range offered in specific speed grades and  
configurations. Contact factory for more information.  
512K x 18  
256K x 32  
256K x 36  
MT58L512L18P  
MT58L256L32P  
MT58L256L36P  
2.5V I/O  
512K x 18  
256K x 32  
256K x 36  
MT58L512V18P  
MT58L256V32P  
MT58L256V36P  
GENERAL DESCRIPTION  
The Micron® SyncBurstSRAM family employs  
high-speed, low-power CMOS designs that are fabri-  
cated using an advanced CMOS process.  
• Packages  
100-pin TQFP (2-chip enable)  
100-pin TQFP (3-chip enable)  
165-pin, 13mm x 15mm FBGA  
• Operating Temperature Range  
Commercial (0°C to +70°C)  
Industrial (-40°C to +85°C)**  
T
S
F*  
Micron’s 8Mb SyncBurst SRAMs integrate a 512K x  
18, 256K x 32, or 256K x 36 SRAM core with advanced  
synchronous peripheral circuitry and a 2-bit burst  
counter. All synchronous inputs pass through registers  
controlled by a positive-edge-triggered single-clock in-  
put (CLK). The synchronous inputs include all ad-  
dresses, all data inputs, active LOW chip enable (CE#),  
two additional chip enables for easy depth expansion  
(CE2, CE2#), burst control inputs (ADSC#, ADSP#,  
ADV#), byte write enables (BWx#) and global write  
None  
IT  
Part Number Example:  
MT58L512L18PT-6  
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM  
MT58L512L18P_C.p65 – Rev. 2/02  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
1
©2002, Micron Technology, Inc.  

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