Datasheet > MT57V1MH18AF-7.5

MT57V1MH18AF-7.5

更新时间： 2024-01-14 04:41:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		双倍数据速率静态存储器
页数	文件大小	规格书
25页	374K
描述
DDR SRAM, 1MX18, 3.6ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165

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MT57V1MH18AF-7.5 数据手册

1 MEG x 18, 512 x 36

2.5V VDD, HSTL, PIPELINED DDRb2 SRAM

MT57V1MH18A

MT57V512H36A

18Mb DDR SRAM

2-Word Burst

Features

Figure 1: 165-Ball FBGA

•

Fast cycle times

Pipelined, double data rate operation

Single 2.5V ±±.1V power supply (VDD)

Separate isolated output buffer supply (VDDQ)

JEDEC-standard 1.5V to 1.8V (±±.1V) HSTL I/O

User-selectable trip point with VREF

HSTL programmable impedance outputs

synchronized to optional dual-data clocks

•

Optional-use echo clocks (CQ and CQ#) for flexible

receive data synchronization

•

JTAG boundary scan

Fully-static design for reduced-power standby

Clock-stop capability

Common data inputs and data outputs

Low-control ball count

Internally self-timed, registered LATE WRITE cycles

Linear burst order with four-tick burst counter

13mm x 15mm, 1mm pitch, 11 x 15 grid FBGA

package

Table 1:

Valid Part Numbers

PART NUMBER

DESCRIPTION

MT57V1MH18AF-xx

MT57V512H36AF-xx

1 Meg x 18, DDRb2 SRAM

512K x 36, DDRb2 SRAM

•

Full data coherency, providing most current data

General Description

The Micron^®DDR synchronous SRAM employs

high-speed, low-power CMOS designs using an

advanced 6T CMOS process.

Options

Marking¹

•

Clock Cycle Timing

5ns (2±± MHz)

6ns (167 MHz)

7.5ns (133 MHz)

-5

-6

-7.5

The DDR SRAM integrates an 18Mb SRAM core with

advanced synchronous peripheral circuitry and a 2-bit

burst counter. All synchronous inputs pass through

registers controlled by an input clock pair (K and K#)

and are latched on the rising edge of K and K#. The

synchronous inputs include all addresses, all data

inputs, active LOW load (LD#) and read/write (R/W#).

Write data is registered on the rising edges of both K

and K#. Read data is driven on the rising edge of C and

C# if provided, or on the rising edge of K and K#, if C

and C# are not provided.

Asynchronous inputs include impedance match

(ZQ). Synchronous data outputs (Q) are closely

matched to the two echo clocks (CQ and CQ#), which

can be used as data receive clocks. Output data clocks

(C and C#) are also provided for maximum system

clocking and data synchronization flexibility.

•

Configurations

1 Meg x 18

MT57V1MH18A

MT57V512H36A

512K x 36

•

Operating Temperature Range

Commercial (±°C ? T_A? 7±°C)

None

Package

165-ball, 13mm x 15mm FBGA

NOTE:

1. A Part Marking Guide for the FBGA devices can be found on

Micron’s Web site—http://www.micron.com/numberguide.

18Mb: 2.5V VDD, HSTL, Pipelined DDRb2 SRAM

MT57V1MH18A_16_F.fm – Rev. F, Pub. 3/03

12 3 4 5 6 7...25

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与MT57V1MH18AF-7.5相关器件

型号	品牌	描述	获取价格	数据表
MT57V1MH18EF-5	CYPRESS	DDR SRAM, 1MX18, 2.4ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165	获取价格
MT57V1MH18EF-6	CYPRESS	DDR SRAM, 1MX18, 3ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165	获取价格
MT57V1MH18EF-7.5	CYPRESS	DDR SRAM, 1MX18, 3.6ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165	获取价格
MT57V256H36PF-3.3	CYPRESS	DDR SRAM, 256KX36, 1.8ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165	获取价格
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