Datasheet > MT55L64L32P1T-6

MT55L64L32P1T-6

更新时间： 2024-01-15 23:49:34

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
17页	214K
描述
ZBT SRAM, 64KX32, 3.5ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100

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技术参数
数据手册

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MT55L64L32P1T-6 技术参数

生命周期：	Transferred	零件包装代码：	QFP
包装说明：	LQFP,	针数：	100
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.55
最长访问时间：	3.5 ns	JESD-30 代码：	R-PQFP-G100
长度：	20 mm	内存密度：	2097152 bit
内存集成电路类型：	ZBT SRAM	内存宽度：	32
功能数量：	1	端子数量：	100
字数：	65536 words	字数代码：	64000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	64KX32
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
宽度：	14 mm	Base Number Matches：	1

MT55L64L32P1T-6 数据手册

2Mb: 128K x 18, 64K x 32/36

3.3V I/O, PIPELINED ZBT SRAM

MT55L128L18P1, MT55L64L32P1,

MT55L64L36P1

2Mb

ZBT SRAM

™

3.3V VDD, 3.3V I/O

FEATURES

• High frequency and 100 percent bus utilization

• Fast cycle times: 6ns, 7.5ns and 10ns

• Single +3.3V ±5% power supply

100-Pin TQFP**

(D-1)

• Advanced control logic for minimum control signal

interface

• Individual BYTE WRITE controls may be tied LOW

• Single R/ W# (read/ write) control pin

• CKE# pin to enable clock and suspend operations

• Three chip enables for simple depth expansion

• Clock-controlled and registered addresses, data I/ Os

and control signals

• Internally self-timed, fully coherent WRITE

• Internally self-timed, registered outputs to eliminate

the need to control OE#

• SNOOZE MODE for reduced-power standby

• Common data inputs and data outputs

• Linear or Interleaved Burst Modes

• Burst feature (optional)

**JEDEC-standard MS-026 BHA (LQFP).

• Pin/ function compatibility with 4Mb, 8Mb and 16Mb

ZBT SRAM family

• Automatic power-down

GENERAL DESCRIPTION

TheMicron ZeroBusTurnaround^™(ZBT^™)SRAM family

employs high-speed, low-power CMOS designs using an

advanced CMOS process.

OPTIONS

MARKING

• Timing (Access/ Cycle/ MHz)

3.5ns/ 6ns/ 166 MHz

4.2ns/ 7.5ns/ 133 MHz

5ns/ 10ns/ 100 MHz

The MT55L128L18P1 and MT55L64L32/ 36P1 SRAMs

integrate a 128K x 18, 64K x 32, or 64K x 36 SRAM core with

advanced synchronous peripheral circuitry and a 2-bit

burst counter. These SRAMs are optimized for 100 percent

bus utilization, eliminating any turnaround cycles when

transitioning from READ to WRITE, or vice versa. All

synchronous inputs pass through registers controlled by a

positive-edge-triggered single clock input (CLK). The

synchronous inputs include all addresses, all data inputs,

chip enable (CE#), two additional chip enables for easy

depth expansion (CE2, CE2#), cycle start input (ADV/

LD#), synchronous clock enable (CKE#), byte write enables

(BWa#, BWb#, BWc# and BWd#) and read/ write (R/ W#).

Asynchronous inputs include the output enable (OE#,

which may be tied LOW for control signal minimization),

clock (CLK) and snooze enable (ZZ, which may be tied

LOW if unused). There is also a burst mode pin (MODE)

that selects between interleaved and linear burst modes.

MODEmay be tied HIGH,LOW or left unconnected ifburst

is unused. The data-out (Q), enabled by OE#, is registered

by the rising edge of CLK. WRITE cycles can be from one to

four bytes wide as controlled by the write control inputs.

-6

-7.5

-10

• Configurations

128K x 18

MT55L128L18P1

MT55L64L32P1

MT55L64L36P1

64K x 32

64K x 36

• Package

100-pin TQFP

• Temperature

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

None

• Part Number Example: MT55L128L18P1T-10 T

*Under consideration.

2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM

MT55L128L18P1.p65 – Rev. 6/99

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1999, Micron Technology, Inc.

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc.,

and the architecture is supported by Micron Technology, Inc., and Motorola Inc.

Micron is a registered trademark of Micron Technology, Inc.

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与MT55L64L32P1T-6相关器件

型号	品牌	描述	获取价格	数据表
MT55L64L32P1T-7.5	CYPRESS	ZBT SRAM, 64KX32, 4.2ns, CMOS, PQFP100, TQFP-100	获取价格
MT55L64L36F1T-10	CYPRESS	ZBT SRAM, 64KX36, 7.5ns, CMOS, PQFP100, TQFP-100	获取价格
MT55L64L36F1T-12	CYPRESS	ZBT SRAM, 64KX36, 9ns, CMOS, PQFP100, TQFP-100	获取价格
MT55L64L36P1F-10	CYPRESS	ZBT SRAM, 64KX36, 5ns, CMOS, PBGA165, FBGA-165	获取价格
MT55L64L36P1F-7.5	CYPRESS	ZBT SRAM, 64KX36, 4.2ns, CMOS, PBGA165, FBGA-165	获取价格
MT55L64L36P1T-10	CYPRESS	ZBT SRAM, 64KX36, 5ns, CMOS, PQFP100, TQFP-100	获取价格

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