Datasheet > MT55L64L32P1F-7.5

MT55L64L32P1F-7.5

更新时间： 2023-02-15 00:00:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
23页	478K
描述
ZBT SRAM, 64KX32, 4.2ns, CMOS, PBGA165, FBGA-165

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MT55L64L32P1F-7.5 数据手册

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2Mb : 128K x 18, 64K x 32/36

3.3V I/O, PIPELINED ZBT SRAM

MT55L128L18P1, MT55L64L32P1,

MT55L64L36P1

2Mb

ZBT^®SRAM

3.3V VDD, 3.3V I/O

FEATURES

• High frequency and 100 percent bus utilization

• Fast cycle times: 7.5ns and 10ns

• Single +3.3V 5ꢀ poꢁer supply

• Advanced control logic for minimum control

signal interface

100-Pin TQFP**

• Individual BYTE WRITE controls may be tied LOW

• Single R/W# (read/ꢁrite) control pin

• CKE# pin to enable clock and suspend operations

• Three chip enables for simple depth expansion

• Clock-controlled and registered addresses, data

I/Os and control signals

• Internally self-timed, fully coherent WRITE

• Internally self-timed, registered outputs eliminate

the need to control OE#

• SNOOZE MODE for reduced-poꢁer standby

• Common data inputs and data outputs

• Linear or Interleaved Burst Modes

• Burst feature (optional)

165-Pin FBGA

(Preliminary Package Data)

• Pin/function compatibility ꢁith 4Mb, 8Mb, and

16Mb ZBT SRAM

• 100-pin TQFP package

• 165-pin FBGA package

• Automatic poꢁer-doꢁn

OPTIONS

MARKING

• Timing (Access/Cycle/MHz)

4.2ns/7.5ns/133 MHz

5ns/10ns/100 MHz

-7.5

-10

**JEDEC-standard MS-026 BHA (LQFP).

• Configurations

128K x 18

MT55L128L18P1

MT55L64L32P1

MT55L64L36P1

GENERAL DESCRIPTION

64K x 32

64K x 36

The Micron^®Zero Bus Turnaround^™(ZBT^®) SRAM

family employs high-speed, loꢁ-poꢁer CMOS designs

using an advanced CMOS process.

• Package

TheMT55L128L18P1andMT55L64L32/36P1SRAMs

integrate a 128K x 18, 64K x 32, or 64K x 36 SRAM core

ꢁith advanced synchronous peripheral circuitry and a

2-bit burst counter. These SRAMs are optimized for 100

percent bus utilization, eliminating turnaround cycles

for READ to WRITE, or WRITE to READ, transitions. All

synchronous inputs pass through registers controlled

by a positive-edge-triggered single clock input (CLK).

The synchronous inputs include all addresses, all data

inputs, chip enable (CE#), tꢁo additional chip enables

for easy depth expansion (CE2, CE2#), cycle start input

100-pin TQFP

165-pin FBGA

• Temperature

Commercial (0°C to +70°C)

None

Part Number Example:

MT55L128L18P1T-10*

* A Part Marking Guide for the FBGA devices can be found on Micron’s

ꢁebsite—http://ꢁꢁꢁ.micronsemi.com/support/index.html.

2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM

MT55L128L18P1_2.p65 – Rev. 8/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

12 3 4 5 6 7...23

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STM32F103C8T6 替代型号

型号	品牌	替代类型	描述	数据表

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