18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
MT55L1MY18P, MT55V1MV18P,
MT55L512Y32P, MT55V512V32P,
MT55L512Y36P, MT55V512V36P
3.3V VDD, 3.3V or 2.5V I/O; 2.5V VDD, 2.5V I/O
18Mb ZBT® SRAM
Features
Figure 1: 100-Pin TQFP
JEDEC-Standard MS-026 BHA (LQFP)
•
•
•
High frequency and 100 percent bus utilization
Single 3.3V ±± percent or 2.±V ±± percent power supply
Separate 3.3V ±± percent or 2.±V ±± percent isolated
output buffer supply (VDDQ)
•
Advanced control logic for minimum control signal
interface
•
•
•
•
•
Individual byte write controls may be tied LOW
Single R/W# (read/write) control pin/ball
CKE# pin/ball to enable clock and suspend operations
Three chip enables for simple depth expansion
Clock-controlled and registered addresses, data
I/Os, and control signals
Internally self-timed, fully coherent WRITE
Internally self-timed, registered outputs to eliminate
the need to control OE#
•
•
•
•
•
•
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SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Linear or Interleaved Burst Modes
Figure 2: 165-Ball FBGA
JEDEC-Standard MS-216 (Var. CAB-1)
Burst feature (optional)
Pin and ball/function compatibility with 2Mb, 4Mb,
and 8Mb ZBT SRAM
TQFP
Options
Marking
•
Timing (Access/Cycle/MHz)
3.2ns/±ns/200 MHz
3.±ns/6ns/166 MHz
4.2ns/7.±ns/133 MHz
±ns/10ns/100 MHz
Configurations
3.3V VDD, 3.3V, or 2.±V I/O
1 Meg x 18
-±
-6
-7.±
-10
•
MT±±L1MY18P
MT±±L±12Y32P
MT±±L±12Y36P
Part Number Example:
±12K x 32
±12K x 36
MT55L512Y36PT-10
2.±V VDD, 2.±V I/O
1 Meg x 18
±12K x 32
±12K x 36
Packages
100-pin TQFP
MT±±V1MV18P
MT±±V±12V32P
MT±±V±12V36P
General Description
The Micron® Zero Bus Turnaround™ (ZBT®) SRAM
family employs high-speed, low-power CMOS designs
using an advanced CMOS process.
•
•
T
F1
Micron’s 18Mb ZBT SRAMs integrate a 1 Meg x 18,
±12K x 32, or ±12K x 36 SRAM core with advanced syn-
16±-ball, 13mm x 1±mm FBGA
Operating Temperature Range
chronous peripheral circuitry and
a 2-bit burst
Commercial (0ºC
?
TA
?
+70ºC)
None
IT2
counter. These SRAMs are optimized for 100 percent
bus utilization, eliminating any turnaround cycles for
READ to WRITE, or WRITE to READ, transitions. All
synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input (CLK).
The synchronous inputs include all addresses, all data
inputs, chip enable (CE#), two additional chip enables
Industrial (-40ºC
?
TA
?
+8±ºC)
NOTE:
1. A Part Marking Guide for the FBGA devices can be found on
Micron’s Web site—http://www.micron.com/numberguide.
2. Contact Factory for availability of Industrial Temperature
devices.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
©2003 Micron Technology, Inc.
1
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
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