18Mb: 1 MEG x 18, 512K x 32/36
FLOW-THROUGH ZBT SRAM
MT55L1MY18F, MT55V1MV18F,
MT55L512Y32F, MT55V512V32F,
MT55L512Y36F, MT55V512V36F
3.3V VDD, 3.3V or 2.5V I/O; 2.5V VDD, 2.5V I/O
18Mb ZBT® SRAM
Features
Figure 1: 100-Pin TQFP
JEDEC-Standard MS-026 BHA (LQFP)
•
•
High frequency and 100 percent bus utilization
Single 3.3V ±± percent or 2.±V ±± percent power
supply
•
•
Separate 3.3V ±± percent or 2.±V ±± percent isolated
output buffer supply (VDDQ)
Advanced control logic for minimum control signal
interface
•
•
•
Individual byte write controls may be tied LOW
Single R/W# (read/write) control pin/ball
CKE# pin/ball to enable clock and suspend
operations
Three chip enables for simple depth expansion
Clock-controlled and registered addresses, data
I/Os, and control signals
•
•
•
•
Internally self-timed, fully coherent write
Internally self-timed, registered outputs to
eliminate the need to control OE#
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Linear or Interleaved Burst Modes
Burst feature (optional)
Figure 2: 165-Ball FBGA
JEDEC-Standard MS-216 (Var. CAB-1)
•
•
•
•
•
Pin and ball/function compatibility with 2Mb, 4Mb,
and 8Mb ZBT SRAM
TQFP
Options
Marking
•
Timing (Access/Cycle/MHz)
6.±ns/8.8ns/113 MHz
7.±ns/10ns/100 MHz
8.±ns/11ns/90 MHz
Configurations
-8.8
-10
-11
•
Part Number Example:
3.3V VDD, 3.3V or 2.±V I/O
1 Meg x 18
±12K x 32
±12K x 36
2.±V VDD, 2.±V I/O
1 Meg x 18
±12K x 32
±12K x 36
Packages
100-pin TQFP
16±-ball, 13mm x 1±mm FBGA
Operating Temperature Range
MT±±L1MY18F
MT±±L±12Y32F
MT±±L±12Y36F
MT55L512Y36FT-11
General Description
The Micron® Zero Bus Turnaround™ (ZBT®) SRAM
family employs high-speed, low-power CMOS designs
using an advanced CMOS process.
MT±±V1MV18F
MT±±V±12V32F
MT±±V±12V36F
•
•
Micron’s 18Mb ZBT SRAMs integrate a 1 Meg x 18,
±12K x 32, or ±12K x 36 SRAM core with advanced syn-
chronous peripheral circuitry and
counter. These SRAMs are optimized for 100 percent
bus utilization, eliminating any turnaround cycles for
READ to WRITE, or WRITE to READ, transitions. All
synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input (CLK).
The synchronous inputs include all addresses, all data
inputs, chip enable (CE#), two additional chip enables
T
F1
a 2-bit burst
Commercial (0ºC
?
T
?
+70ºC)
None
IT2
A
Industrial (-40ºC
?
TA
?
+8±ºC)
NOTE:
1. A Part Marking Guide for the FBGA devices can be found on
Micron’s Web site—http://www.micron.com/numberguide.
2. Contact Factory for availability of Industrual Temperature
devices.
18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM
MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03
©2003 Micron Technology, Inc.
1
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
5秒后页面跳转
PCF8574资料解读：主要参数分析、引脚说明
AD637数据手册解读：主要特性、引脚及其功能解读、电气参数
ADUM1201资料手册解读：参数分析、引脚说明、应用分析
一文带你了解压敏电阻器在直流电路中的过压保护作用
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
