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MT55L256L18P1T-10A PDF预览

MT55L256L18P1T-10A

更新时间: 2023-01-15 00:00:00
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
26页 455K
描述
ZBT SRAM, 256KX18, 5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100

MT55L256L18P1T-10A 数据手册

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PRELIMINARY  
4Mb : 256K x 18, 128K x 32/36  
PIPELINED ZBT SRAM  
4Mb ZBT™  
SRAM  
MT55L256L18P1, MT55L256V18P1,  
MT55L128L32P1, MT55L128V32P1,  
MT55L128L36P1, MT55L128V36P1  
3.3V VDD, 3.3V o r 2.5V I/O  
WITH SMART ZBT OPTION  
FEATURES  
• SMART ZBT™ option to minimize potential bus  
contention  
100-Pin TQFP**  
• High frequency and 100 percent bus utilization  
• Fast cycle times: 6ns, 7.5ns and 10ns  
• Single +3.3V ±5% power supply (VDD)  
• Separate +3.3V or +2.5V isolated output buffer  
supply (VDDQ)  
• Advanced control logic for minimum control  
signal interface  
• Individual BYTE WRITE controls may be tied LOW  
• Single R/W# (read/write) control pin  
• CKE# pin to enable clock and suspend operations  
• Three chip enables for simple depth expansion  
• Clock-controlled and registered addresses, data  
I/Os and control signals  
• Internally self-timed, fully coherent WRITE  
• Internally self-timed, registered outputs to  
eliminate the need to control OE#  
• SNOOZE MODE for reduced-power standby  
• Common data inputs and data outputs  
• Linear or interleaved burst modes  
• Burst feature (optional)  
119-Pin BGA  
• Pin/function compatibility with 2Mb, 8Mb and  
16Mb ZBT SRAM family  
• Automatic power-down  
OPTIONS  
MARKING  
• Timing (Access/Cycle/MHz)  
4ns/6ns/166 MHz  
4.2ns/7.5ns/133 MHz  
5ns/10ns/100 MHz  
• Configurations  
3.3V I/O  
-6  
-7.5*  
-10*  
**JEDEC-standard MS-026 BHA (LQFP).  
256K x 18  
128K x 32  
128K x 36  
MT55L256L18P1  
MT55L128L32P1  
MT55L128L36P1  
GENERAL DESCRIPTION  
The Micron® Zero Bus Turnaround(ZBT) SRAM  
family employs high-speed, low-power CMOS designs  
using an advanced CMOS process.  
2.5V I/O  
256K x 18  
128K x 32  
128K x 36  
MT55L256V18P1  
MT55L128V32P1  
MT55L128V36P1  
The SMART ZBT feature enhances the ability of the  
SRAM to run in systems with minimal transition time  
on the data bus, whether using multiple SRAMs or  
complementing ASIC designs.  
• Package  
100-pin TQFP  
119-pin, 14mm x 22mm BGA  
T
B
Micron’sSMART ZBTfeatureallowsthetKHQX1(clock  
HIGH tooutputvalid)toadapttothesystemclock, thus  
reducing contention issues. The SMART ZBT will drive  
the bus turn-on later than the traditional ZBT.  
*SMART ZBT option available.  
Part Number Example:  
MT55L256L18P1T-10A  
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM  
MT55L256L18P1.p65 – Rev. 3/00  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2000, Micron Technology, Inc.  
1

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