4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
MT55L256L18P1, MT55L256V18P1,
MT55L128L32P1, MT55L128V32P1,
MT55L128L36P1, MT55L128V36P1
4Mb
ZBT® SRAM
3.3V VDD, 3.3V or 2.5V I/O
FEATURES
1
100-PinTQFP
• High frequency and 100 percent bus utilization
• Fast cycle times: 6ns, 7.5ns and 10ns
• Single +3.3V 5ꢀ poꢁer supply ꢂVDD)
• Separate +3.3V or +2.5V isolated output buffer
supply ꢂVDDQ)
• Advanced control logic for minimum control signal
interface
• Individual BYTE WRITE controls may be tied LOW
• Single R/W# ꢂread/ꢁrite) control pin
• CKE# pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• Clock-controlled and registered addresses, data
I/Os and control signals
• Internally self-timed, fully coherent WRITE
• Internally self-timed, registered outputs to
eliminate the need to control OE#
• SNOOZE MODE for reduced-poꢁer standby
• Common data inputs and data outputs
• Linear or interleaved burst modes
• Burst feature ꢂoptional)
165-PinFBGA
• Pin/function compatibility ꢁith 2Mb, 8Mb, and
16Mb ZBT SRAM family
• Automatic poꢁer-doꢁn
• 165-pin FBGA package
• 100-pin TQFP package
OPTIONS
MARKING
• Timing ꢂAccess/Cycle/MHz)
3.5ns/6ns/166 MHz
4.2ns/7.5ns/133 MHz
5ns/10ns/100 MHz
• Configurations
3.3V I/O
NOTE: 1. JEDEC-standardMS-026BHA(LQFP).
-6
-7.5
-10
* A Part Marking Guide for the FBGA devices can be found on Micron’s
Web site—http://ꢁꢁꢁ.micron.com/support/index.html.
** Industrial temperature range offered in specific speed grades and
configurations. Contact factory for more information.
256K x 18
128K x 32
128K x 36
MT55L256L18P1
MT55L128L32P1
MT55L128L36P1
2.5V I/O
GENERALDESCRIPTION
The Micron® Zero Bus Turnaround™ ꢂZBT®) SRAM
family employs high-speed, loꢁ-poꢁer CMOS designs
using an advanced CMOS process.
256K x 18
128K x 32
128K x 36
MT55L256V18P1
MT55L128V32P1
MT55L128V36P1
• Package
Micron’s 4Mb ZBT SRAMs integrate a 256K x 18,
128K x 32, or 128K x 36 SRAM core ꢁith advanced syn-
chronous peripheral circuitry and a 2-bit burst counter.
These SRAMs are optimized for 100 percent bus utiliza-
tion, eliminating any turnaround cycles ꢁhen
transitioning from READ to WRITE, or vice versa. All
synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input ꢂCLK).
100-pin TQFP
165-pin FBGA
• Operating Temperature Range
Commercial ꢂ0°C to +70°C)
Industrial ꢂ-40°C to +85°C)**
T
F*
None
IT
Part Number Example:
MT55L256L18P1T-10
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
©2003,MicronTechnology,Inc.
1
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.