NOTRECOMENDEDFORNEWDESIGNS
2Mb: 128K x 18, 64K x 32/36
3.3V I/O, PIPELINED ZBT SRAM
MT55L128L18P1, MT55L64L32P1,
MT55L64L36P1
2Mb
ZBT® SRAM
3.3V VDD, 3.3V I/O
FEATURES
• High frequency and 100 percent bus utilization
• Fast cycle times: 7.5ns and 10ns
• Single +3.3V 5ꢀ poꢁer supply
100-PinTQFP*
• Advanced control logic for minimum control signal
interface
• Individual BYTE WRITE controls may be tied LOW
• Single R/W# (read/ꢁrite) control pin
• CKE# pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• Clock-controlled and registered addresses, data
I/Os and control signals
• Internally self-timed, fully coherent WRITE
• Internally self-timed, registered outputs eliminate
the need to control OE#
• SNOOZE MODE for reduced-poꢁer standby
• Common data inputs and data outputs
• Linear or Interleaved Burst Modes
• Burst feature (optional)
• Pin/function compatibility ꢁith 4Mb, 8Mb, and
16Mb ZBT SRAM
*JEDEC-standard MS-026 BHA (LQFP).
GENERALDESCRIPTION
The Micron® Zero Bus Turnaround™ (ZBT®) SRAM
family employs high-speed, loꢁ-poꢁer CMOS designs
using an advanced CMOS process.
• 100-pin TQFP package
• Automatic poꢁer-doꢁn
The MT55L128L18P1 and MT55L64L32/36P1
SRAMs integrate a 128K x 18, 64K x 32, or 64K x 36 SRAM
core ꢁith advanced synchronous peripheral circuitry
and a 2-bit burst counter. These SRAMs are optimized
for 100 percent bus utilization, eliminating turnaround
cycles for READ to WRITE, or WRITE to READ, transi-
tions. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single clock in-
put (CLK). The synchronous inputs include all ad-
dresses, all data inputs, chip enable (CE#), tꢁo addi-
tional chip enables for easy depth expansion (CE2,
CE2#), cycle start input (ADV/LD#), synchronous clock
enable (CKE#), byte ꢁrite enables (BWa#, BWb#, BWc#
and BWd#) and read/ꢁrite (R/W#).
OPTIONS
MARKING
• Timing (Access/Cycle/MHz)
4.2ns/7.5ns/133 MHz
5ns/10ns/100 MHz
-7.5
-10
• Configurations
128K x 18
MT55L128L18P1
MT55L64L32P1
MT55L64L36P1
64K x 32
64K x 36
• Package
100-pin TQFP
T
Asynchronous inputs include the output enable
(OE#, ꢁhich may be tied LOW for control signal minimi-
zation), clock (CLK) and snooze enable (ZZ, ꢁhich may
be tied LOW if unused). There is also a burst mode pin
(MODE) that selects betꢁeen interleaved and linear
burst modes. MODE may be tied HIGH, LOW or left
unconnected if burst is unused. The data-out (Q), en-
abled by OE#, is registered by the rising edge of CLK.
WRITE cycles can be from one to four bytes ꢁide as
controlled by the ꢁrite control inputs.
• Temperature
Commercial (0°C to +70°C)
None
Part Number Example:
MT55L128L18P1T-10
2Mb:128Kx18, 64Kx32/363.3VI/O, PipelinedZBTSRAM
MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02
©2002,MicronTechnology,Inc.
1
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.