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MT41K64M16TW-107 IT PDF预览

MT41K64M16TW-107 IT

更新时间: 2024-10-01 17:00:39
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镁光 - MICRON 动态存储器双倍数据速率
页数 文件大小 规格书
215页 16514K
描述
DDR3 SDRAM

MT41K64M16TW-107 IT 数据手册

 浏览型号MT41K64M16TW-107 IT的Datasheet PDF文件第2页浏览型号MT41K64M16TW-107 IT的Datasheet PDF文件第3页浏览型号MT41K64M16TW-107 IT的Datasheet PDF文件第4页浏览型号MT41K64M16TW-107 IT的Datasheet PDF文件第5页浏览型号MT41K64M16TW-107 IT的Datasheet PDF文件第6页浏览型号MT41K64M16TW-107 IT的Datasheet PDF文件第7页 
1Gb: x4, x8, x16 DDR3L SDRAM  
Description  
DDR3L SDRAM  
MT41K256M4 – 32 Meg x 4 x 8 banks  
MT41K128M8 – 16 Meg x 8 x 8 banks  
MT41K64M16 – 8 Meg x 16 x 8 banks  
• Write leveling  
• Multipurpose register  
Description  
The 1.35V DDR3L SDRAM device is a low-voltage ver-  
sion of the 1.5V DDR3 SDRAM device. Refer to the  
DDR3 (1.5V) SDRAM data sheet specifications when  
running in 1.5V compatible mode.  
• Output driver calibration  
Options1  
• Configuration  
Marking  
– 256 Meg x 4  
– 128 Meg x 8  
– 64 Meg x 16  
256M4  
128M8  
64M16  
Features  
• VDD = VDDQ = +1.35V (1.283V to 1.45V)  
• Backward compatible to VDD = VDDQ = 1.5V ±0.075V  
• Differential bidirectional data strobe  
• 8n-bit prefetch architecture  
• FBGA package (Pb-free) – x4, x8  
– 78-ball FBGA (8mm x 11.5mm) Rev.  
G
– 78-ball FBGA (8mm x 10.5mm) Rev. J  
• FBGA package (Pb-free) – x16  
– 96-ball FBGA (8mm x 14mm) Rev. G  
– 96-ball FBGA (8mm x 14mm) Rev. J  
• Timing – cycle time  
– 1.07ns @ CL = 13 (DDR3-1866)  
– 1.25ns @ CL = 11 (DDR3-1600)  
– 1.5ns @ CL = 9 (DDR3-1333)  
– 1.87ns @ CL = 7 (DDR3-1066)  
• Operating temperature  
– Commercial (0°C TC +95°C)  
– Industrial (–40°C TC +95°C)  
• Revision  
JP  
• Differential clock inputs (CK, CK#)  
• 8 internal banks  
DA  
• Nominal and dynamic on-die termination (ODT)  
for data, strobe, and mask signals  
• Programmable CAS (READ) latency (CL)  
• Programmable CAS additive latency (AL)  
• Programmable CAS (WRITE) latency (CWL)  
• Fixed burst length (BL) of 8 and burst chop (BC) of 4  
(via the mode register set [MRS])  
• Selectable BC4 or BL8 on-the-fly (OTF)  
• Self refresh mode  
JT  
TW  
-107  
-125  
-15E  
-187E  
None  
IT  
:G / :J  
• TC of 95°C  
– 64ms, 8192-cycle refresh up to 85°C  
– 32ms, 8192-cycle refresh at >85°C to 95°C  
• Self refresh temperature (SRT)  
1. Not all options listed can be combined to  
define an offered product. Use the part  
catalog search on http://www.micron.com  
for available offerings.  
Note:  
• Automatic self refresh (ASR)  
Table 1: Key Timing Parameters  
Speed Grade  
-1071, 2, 3  
-1251, 2  
Data Rate (MT/s)  
Target tRCD-tRP-CL  
tRCD (ns)  
13.91  
13.75  
13.5  
tRP (ns)  
13.91  
13.75  
13.5  
CL (ns)  
13.91  
13.75  
13.5  
1866  
1600  
1333  
1066  
13-13-13  
11-11-11  
9-9-9  
-15E1  
187E  
7-7-7  
13.1  
13.1  
13.1  
1. Backward compatible to 1066, CL = 7 (-187E).  
2. Backward compatible to 1333, CL = 9 (-15E).  
3. Backward compatible to 1600, CL = 11 (-125).  
Notes:  
PDF: CCMTD-1725822587-774  
1Gb_DDR3L.pdf - Rev. L EN 9/18  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
© 2008 Micron Technology, Inc. All rights reserved.  
1
Products and specifications discussed herein are subject to change by Micron without notice.  

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