Datasheet > MT41K128M16JT-125 IT

MT41K128M16JT-125 IT

更新时间： 2024-03-03 10:09:13

品牌	Logo	应用领域
镁光 - MICRON		动态存储器双倍数据速率
页数	文件大小	规格书
215页	3162K
描述
2Gb: x4, x8, x16 DDR3 SDRAM

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数据手册

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2Gb: x4, x8, x16 DDR3 SDRAM

Features

DDR3 SDRAM

MT41J512M4 – 64 Meg x 4 x 8 Banks

MT41J256M8 – 32 Meg x 8 x 8 Banks

MT41J128M16 – 16 Meg x 16 x 8 Banks

Options¹

Marking

Features

• V_DD= V_DDQ= 1.5V ±±.±05V

• 1.5V center-terminated push/pull I/O

• Differential bidirectional data strobe

• 8n-bit prefetch architecture

• Differential clock inputs (CK, CK#)

• 8 internal banks

• Nominal and dynamic on-die termination (ODT)

for data, strobe, and mask signals

• Programmable CAS READ latency (CL)

• Posted CAS additive latency (AL)

• Programmable CAS WRITE latency (CWL) based on

^tCK

• Fixed burst length (BL) of 8 and burst chop (BC) of 4

(via the mode register set [MRS])

• Selectable BC4 or BL8 on-the-fly (OTF)

• Self refresh mode

• Configuration

– 512 Meg x 4

– 256 Meg x 8

– 128 Meg x 16

512M4

256M8

128M16

• FBGA package (Pb-free) – x4, x8

– 08-ball (8mm x 1±.5mm) Rev. K

– 08-ball (8mm x 1±.5mm) Rev. N

• FBGA package (Pb-free) – x16

– 96-ball (8mm x 14mm) Rev. K

– 96-ball (8mm x 14mm) Rev. N

• Timing – cycle time

– 938ps @ CL = 14 (DDR3-2133)

– 1.±0ns @ CL = 13 (DDR3-1866)

– 1.25ns @ CL = 11 (DDR3-16±±)

– 1.5ns @ CL = 9 (DDR3-1333)

– 1.80ns @ CL = 0 (DDR3-1±66)

• Operating temperature

-±93

-1±0

-125

-15E

-180E

• T_Cof ±°C to 95°C

– Commercial (±°C ≤ T_C≤ +95°C)

– Industrial (–4±°C ≤ T_C≤ +95°C)

• Revision

None

:K / :N

– 64ms, 8192 cycle refresh at ±°C to 85°C

– 32ms, 8192 cycle refresh at 85°C to 95°C

• Self refresh temperature (SRT)

• Automatic self refresh (ASR)

• Write leveling

1. Not all options listed can be combined to

define an offered product. Use the part

Note:

• Multipurpose register

• Output driver calibration

catalog search on http://www.micron.com

for available offerings.

Table 1: Key Timing Parameters

Speed Grade

-093^{1, 2, 3, 4}

-107^{1, 2, 3}

-125^{1, 2,}

Data Rate (MT/s)

Target ^tRCD-^tRP-CL

^tRCD (ns)

13.13

13.91

13.75

13.5

^tRP (ns)

13.13

13.91

13.75

13.5

CL (ns)

13.13

13.91

13.75

13.5

2133

1866

1600

1333

1066

14-14-14

13-13-13

11-11-11

9-9-9

-15E^1,

-187E

7-7-7

13.1

1. Backward compatible to 1066, CL = 7 (-187E).

2. Backward compatible to 1333, CL = 9 (-15E).

3. Backward compatible to 1600, CL = 11 (-125).

4. Backward compatible to 1866, CL = 13 (-107).

Notes:

PDF: 09005aef826aaadc

2Gb_DDR3_SDRAM.pdf - Rev. S 02/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

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