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MT41J64M16JT-125G PDF预览

MT41J64M16JT-125G

更新时间: 2024-09-29 01:23:03
品牌 Logo 应用领域
镁光 - MICRON 动态存储器双倍数据速率
页数 文件大小 规格书
214页 2938K
描述
DDR3 SDRAM MT41J256M4 – 32 Meg x 4 x 8 banks MT41J128M8 – 16 Meg x 8 x 8 banks MT41J64M16 – 8 Meg x 16 x 8 banks

MT41J64M16JT-125G 数据手册

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1Gb: x4, x8, x16 DDR3 SDRAM  
Features  
DDR3 SDRAM  
MT41J256M4 – 32 Meg x 4 x 8 banks  
MT41J128M8 – 16 Meg x 8 x 8 banks  
MT41J64M16 – 8 Meg x 16 x 8 banks  
Options1  
Marking  
Features  
• VDD = VDDQ = 1.5V ±±.±05V  
• 1.5V center-terminated push/pull I/O  
• Differential bidirectional data strobe  
• 8n-bit prefetch architecture  
• Differential clock inputs (CK, CK#)  
• 8 internal banks  
• Nominal and dynamic on-die termination (ODT)  
for data, strobe, and mask signals  
• Programmable CAS READ latency (CL)  
• POSTED CAS ADDITIVE latency (AL)  
• Programmable CAS WRITE latency (CWL) based on  
tCK  
• Fixed burst length (BL) of 8 and burst chop (BC) of 4  
(via the mode register set [MRS])  
• Selectable BC4 or BL8 on-the-fly (OTF)  
• Self refresh mode  
• Configuration  
– 256 Meg x 4  
– 128 Meg x 8  
– 64 Meg x 16  
256M4  
128M8  
64M16  
• FBGA package (Pb-free) – x4, x8  
– 08-ball (8mm x 11.5mm) Rev. G  
• FBGA package (Pb-free) – x16  
– 96-ball (8mm x 14mm) Rev. G  
• Timing – cycle time  
– 1.±0ns @ CL = 13 (DDR3-1866)  
– 1.±0ns @ CL = 12 (DDR3-1866)  
– 1.25ns @ CL = 11 (DDR3-16±±)  
– 1.5ns @ CL = 9 (DDR3-1333)  
– 1.80ns @ CL = 0 (DDR3-1±66)  
• Operating temperature  
– Commercial (±°C TC +95°C)  
– Industrial (–4±°C TC +95°C)  
– Automotive (–4±°C TC +1±5°C)  
• Revision  
JP  
JT  
-1±0  
-1±0E  
-125  
-15E  
-180E  
None  
IT  
AT  
• TC of ±°C to 95°C  
– 64ms, 8192 cycle refresh at ±°C to 85°C  
– 32ms, 8192 cycle refresh at 85°C to 95°C  
• Self refresh temperature (SRT)  
• Automatic self refresh (ASR)  
• Write leveling  
G
1. Not all options listed can be combined to  
define an offered product. Use the part  
catalog search on http://www.micron.com  
for available offerings.  
Note:  
• Multipurpose register  
• Output driver calibration  
Table 1: Key Timing Parameters  
Speed Grade  
-1071, 2  
Data Rate (MT/s)  
Target tRCD-tRP-CL  
tRCD (ns)  
13.91  
12.84  
13.75  
13.5  
tRP (ns)  
13.91  
12.84  
13.75  
13.5  
CL (ns)  
13.91  
12.84  
13.75  
13.5  
1866  
1866  
1600  
1333  
1066  
13-13-13  
12-12-12  
11-11-11  
9-9-9  
-107E1, 2  
-1251, 2  
-15E1  
187E  
7-7-7  
13.1  
13.1  
13.1  
1. Backward compatible to 1066, CL = 7 (-187E).  
2. Backward compatible to 1333, CL = 9 (-15E).  
Notes:  
PDF: 09005aef826aa906  
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
1
‹ 2006 Micron Technology, Inc. All rights reserved.  
Products and specifications discussed herein are subject to change by Micron without notice.  

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