Datasheet > MT41J512M4

MT41J512M4

更新时间： 2024-09-28 12:28:31

品牌	Logo	应用领域
镁光 - MICRON		动态存储器双倍数据速率
页数	文件大小	规格书
211页	2907K
描述
2Gb: x4, x8, x16 DDR3 SDRAM Features

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

MT41J512M4 数据手册

2Gb: x4, x8, x16 DDR3 SDRAM

Features

DDR3 SDRAM

MT41J512M4 – 64 Meg x 4 x 8 Banks

MT41J256M8 – 32 Meg x 8 x 8 Banks

MT41J128M16 – 16 Meg x 16 x 8 Banks

Options¹

Marking

Features

• V_DD= V_DDQ= 1.5V ±±.±05V

• 1.5V center-terminated push/pull I/O

• Differential bidirectional data strobe

• 8n-bit prefetch architecture

• Differential clock inputs (CK, CK#)

• 8 internal banks

• Nominal and dynamic on-die termination (ODT)

for data, strobe, and mask signals

• Programmable CAS READ latency (CL)

• Posted CAS additive latency (AL)

• Programmable CAS WRITE latency (CWL) based on

^tCK

• Fixed burst length (BL) of 8 and burst chop (BC) of 4

(via the mode register set [MRS])

• Selectable BC4 or BL8 on-the-fly (OTF)

• Self refresh mode

• Configuration

– 512 Meg x 4

– 256 Meg x 8

– 128 Meg x 16

512M4

256M8

128M16

• FBGA package (Pb-free) – x4, x8

– 08-ball (8mm x 1±.5mm) Rev. M, K

– 08-ball (9mm x 11.5mm) Rev. D

• FBGA package (Pb-free) – x16

– 96-ball (9mm x 14mm) Rev. D

– 96-ball (8mm x 14mm) Rev. K

• Timing – cycle time

– 938ps @ CL = 14 (DDR3-2133)

– 1.±01ns @ CL = 13 (DDR3-1866)

– 1.25ns @ CL = 11 (DDR3-16±±)

– 1.5ns @ CL = 9 (DDR3-1333)

– 1.80ns @ CL = 0 (DDR3-1±66)

• Operating temperature

-±93

-1±0

-125

-15E

-180E

• T_Cof ±°C to 95°C

– Commercial (±°C ≤ T_C≤ +95°C)

– Industrial (–4±°C ≤ T_C≤ +95°C)

• Revision

None

:D/:M/:K

– 64ms, 8192 cycle refresh at ±°C to 85°C

– 32ms, 8192 cycle refresh at 85°C to 95°C

• Self refresh temperature (SRT)

• Write leveling

• Multipurpose register

• Output driver calibration

1. Not all options listed can be combined to

define an offered product. Use the part

Note:

catalog search on http://www.micron.com

for available offerings.

Table 1: Key Timing Parameters

Speed Grade

-093^{1, 2, 3, 4}

-107^{1, 2, 3}

-125^{1, 2,}

Data Rate (MT/s)

Target ^tRCD-^tRP-CL

^tRCD (ns)

13.09

13.91

13.75

13.5

^tRP (ns)

13.09

13.91

13.75

13.5

CL (ns)

13.09

13.91

13.75

13.5

2133

1866

1600

1333

1066

14-14-14

13-13-13

11-11-11

9-9-9

-15E^1,

-187E

7-7-7

13.1

1. Backward compatible to 1066, CL = 7 (-187E).

2. Backward compatible to 1333, CL = 9 (-15E).

3. Backward compatible to 1600, CL = 11 (-125).

4. Backward compatible to 1866, CL = 13 (-107).

Notes:

PDF: 09005aef826aaadc

2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

12 3 4 5 6 7...211

中文翻译

下载PDF

与MT41J512M4相关器件

型号	品牌	获取价格	描述	数据表
MT41J64M16	MICRON	获取价格	DDR3 SDRAM MT41J256M4 â 32 Meg x 4 x 8 bank
MT41J64M16	MDTIC	获取价格	1Gb: x4, x8, x16 DDR3 SDRAM
MT41J64M16JT	MICRON	获取价格	MT41J256M4 â 32 Meg x 4 x 8 banks
MT41J64M16JT-125G	MICRON	获取价格	DDR3 SDRAM MT41J256M4 â 32 Meg x 4 x 8 bank
MT41K128M16JT-107	MICRON	获取价格	2Gb: x4, x8, x16 DDR3L SDRAM
MT41K128M16JT-107 AAT	MICRON	获取价格	MT41K256M8 (32 Meg x 8 x 8 banks), MT41K128M16 (16 Meg x 16 x 8 banks)
MT41K128M16JT-107 IT	MICRON	获取价格	2Gb: x4, x8, x16 DDR3L SDRAM
MT41K128M16JT-125	MICRON	获取价格	2Gb: x4, x8, x16 DDR3L SDRAM
MT41K128M16JT-125 AAT	MICRON	获取价格	MT41K256M8 (32 Meg x 8 x 8 banks), MT41K128M16 (16 Meg x 16 x 8 banks)
MT41K128M16JT-125 AIT	MICRON	获取价格	MT41K256M8 (32 Meg x 8 x 8 banks), MT41K128M16 (16 Meg x 16 x 8 banks)

与MT41J512M4相关文章

塔塔电子与力积电达成技术转让协议，携手建设印度首座晶圆厂
2024-09-29

24
英特尔震撼发布：128核心256线程的至强6性能核处理器
2024-09-29

21
SK海力士量产12层HBM3E，容量高达36GB
2024-09-27

20
意法半导体传感器驱动Sphere，开启沉浸式电影新时代
2024-09-27

32

产品中心

服务支持

精选活动

关于我们

帮助中心

MT41J512M4

MT41J512M4 数据手册

与MT41J512M4相关器件

与MT41J512M4相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MT41J512M4

MT41J512M4 数据手册

与MT41J512M4相关器件

与MT41J512M4相关文章

您还可以找

您在本页遇到什么问题？