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MT40A512M8RH-083E IT PDF预览

MT40A512M8RH-083E IT

更新时间: 2024-03-03 10:08:17
品牌 Logo 应用领域
镁光 - MICRON /
页数 文件大小 规格书
384页 11123K
描述
MT40A512M8, MT40A256M16

MT40A512M8RH-083E IT 数据手册

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4Gb: x8, x16 Automotive DDR4 SDRAM  
Features  
Automotive DDR4 SDRAM  
MT40A512M8, MT40A256M16  
Options1  
Marking  
Features  
• VDD = VDDQ = 1.2V ±±60V  
• VPP = 2.5V –1250V/+2560V  
• On-die, internal, adjustable VREFDQ generation  
• 1.2V pseudo open-drain I/O  
• Refresh 0axi0u0 interval ti0e at TC te0perature  
range:  
– ±40s at –46°C to 85°C  
– 320s at 85°C to 95°C  
– 1±0s at 9±°C to 165°C  
– 80s at 16±°C to 125°C  
• 1± internal banks ( x8): 4 groups of 4 banks each  
• 8 internal banks (x1±): 2 groups of 4 banks each  
• 8n-bit prefetch architecture  
• Progra00able data strobe prea0bles  
• Data strobe prea0ble training  
• Co00and/Address latency (CAL)  
• Multipurpose register read and write capability  
• Write leveling  
• Configuration  
– 512 Meg x 8  
– 25± Meg x 1±  
512M8  
25±M1±  
• BGA package (Pb-free) – x8  
– 78-ball (900 x 16.500) – Rev. B  
– 78-ball (7.500 x 1100) – Rev. F  
• FBGA package (Pb-free) – x1±  
– 9±-ball (900 x 1400) – Rev. B  
– 9±-ball (7.500 x 13.500) – Rev. F  
• Ti0ing – cycle ti0e  
– 6.±25ns @ CL = 22 (DDR4-3266)  
– 6.756ns @ CL = 18 (DDR4-2±±±)  
– 6.833ns @ CL = 1± (DDR4-2466)  
• Auto0otive grade  
RH  
SA, AG  
GE  
LY, AD  
-6±2E  
-675E  
-683E  
A
– AEC-Q166  
– PPAP  
• Operating te0perature  
– Industrial (–46°C TC +95°C)  
– Auto0otive (–46°C TC +165°C)  
– Ultra-high (–46°C TC +125°C)3  
– Revision  
IT  
AT  
UT  
:B :F  
• Self refresh 0ode  
• Low-power auto self refresh (LPASR)  
Te0perature controlled refresh (TCR)  
• Fine granularity refresh  
• Self refresh abort  
• Maxi0u0 power saving  
• Output driver calibration  
• No0inal, park, and dyna0ic on-die ter0ination  
(ODT)  
• Data bus inversion (DBI) for data bus  
• Co00and/Address (CA) parity  
• Databus write cyclic redundancy check (CRC)  
• Per-DRAM addressability  
1. Not all options listed can be combined to  
define an offered product. Use the part cat-  
alog search on http://www.micron.com for  
available offerings.  
Notes:  
2. The ×4 device is not offered and the mode  
is not supported by the x8 or x16 device  
even though some ×4 mode descriptions ex-  
ist in the datasheet.  
3. The UT option use based on automotive us-  
age model. Please contact Micron sales rep-  
resentative if you have questions.  
• Connectivity test  
4. -062E is only available for die Rev. F.  
• Hard post package repair (hPPR) and soft post  
package repair (sPPR) 0odes  
• JEDEC JESD-79-4 co0pliant  
Table 1: Key Timing Parameters  
Speed Grade  
-062E1  
Data Rate (MT/s)  
Target CL-nRCD-nRP  
tAA (ns)  
13.75  
tRCD (ns)  
13.75  
tRP (ns)  
13.75  
13.5  
3200  
2666  
2400  
22-22-22  
18-18-18  
16-16-16  
-075E1  
13.5  
13.5  
-083E  
13.32  
13.32  
13.32  
1. Refer to the Speed Bin Tables for backward compatibility  
Note:  
CCMTD-1725822587-10418  
4gb_auto_ddr4_sdram_z90b_z10B.pdf - Rev. L 03/2021 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
1
‹ 2016 Micron Technology, Inc. All rights reserved.  
Products and specifications discussed herein are subject to change by Micron without notice.  

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