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MT40A512M16TD-062E AAT PDF预览

MT40A512M16TD-062E AAT

更新时间: 2024-03-03 10:09:30
品牌 Logo 应用领域
镁光 - MICRON /
页数 文件大小 规格书
373页 11121K
描述
MT40A1G8, MT40A512M16

MT40A512M16TD-062E AAT 数据手册

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8Gb: x8, x16 Automotive DDR4 SDRAM  
Features  
Automotive DDR4 SDRAM  
MT40A1G8  
MT40A512M16  
Features  
s VDD = VDDQ = 1.2V ά60mV  
s VPP ꢀ ꢁꢂꢃ6 nꢄꢁꢃM6ꢅꢆꢁꢃꢇM6  
s On-die, internal, adjustable VREFDQ generation  
s 1.2V pseudo open-drain I/O  
s Refresh time of 8192-cycle at TC temperature range:  
n ꢈꢉMS AT nꢉꢇιC to 85ιC  
Options1  
s Configuration  
n 1 Gig x 8  
n 512 Meg x 16  
Marking  
1G8  
512M16  
s ꢊꢋꢌBALL &"'! PACKAGE ꢍ0BꢌFREEꢎ n Xꢋ  
n ꢋMM X ꢄꢁMM n 2EVꢂ "  
n ꢊꢂꢃMM X ꢄꢄMM n 2EVꢂ %ꢏ 2  
s ꢐꢈꢌBALL &"'! PACKAGE ꢍ0BꢌFREEꢎ n Xꢄꢈ  
n ꢋMM X ꢄꢉMM n 2EVꢂ "  
n ꢊꢂꢃMM X ꢄꢑꢂꢃMM n 2EVꢂ %  
n ꢊꢂꢃMM X ꢄꢑMM n 2EVꢂ 2  
s 4IMING n CYCLE TIME  
n 0.625ns @ CL = 22 (DDR4-3200)  
n 0.750ns @ CL = 18 (DDR4-2666)  
n 0.833ns @ CL = 16 (DDR4-2400)  
s Product certification  
WE  
SA, AG  
n 32ms at 85ιC to 95ιC  
n 16ms at 95ιC to 105ιC  
n 8ms at 105ιC to 125ιC  
JY  
LY, AD  
TD  
s 16 internal banks (x8): 4 groups of 4 banks each  
s 8 internal banks (x16): 2 groups of 4 banks each  
s 8n-bit prefetch architecture  
s Programmable data strobe preambles  
s Data strobe preamble training  
s Command/Address latency (CAL)  
s Multipurpose register read and write capability  
s Write leveling  
-062E  
-075E  
-083E  
A
n Automotive  
s Operating temperature  
n )NDUSTRIAL ꢍnꢉꢇι ζ TC ζ 95ιC)  
n !UTOMOTIVE ꢍnꢉꢇι ζ TC ζ 105ιC)  
n 5LTRAꢌHIGH ꢍnꢉꢇι ζ TC ζ 125ιC)3  
s Revision  
s Self refresh mode  
IT  
AT  
UT  
s Low-power auto self refresh (LPASR)  
s Temperature controlled refresh (TCR)  
s Fine granularity refresh  
:B, :E, :R  
s Self refresh abort  
s Maximum power saving  
s Output driver calibration  
s Nominal, park, and dynamic on-die termination  
(ODT)  
Notes: 1. Not all options listed can be combined to  
define an offered product. Use the part  
catalog search on http://www.micron.com for  
available offerings.  
2. Extended temperature mode during temperature  
controlled refresh is not supported on 8Gb die  
revision R. Refer to note 2 in table MR4 Definition.  
3. The έ4 device is not offered and the mode is not  
supported by the x8 or x16 device even though  
some έ4 mode descriptions exist in the data sheet.  
4. The UT option use based on automotive usage  
model. Contact Micron sales representative if you  
have questions.  
s Data bus inversion (DBI) for data bus  
s Command/Address (CA) parity  
s Databus write cyclic redundancy check (CRC)  
s Per-DRAM addressability  
s Connectivity test  
s JEDEC JESD-79-4 compliant2  
s sPPR and hPPR capability  
s MBIST-PPR support (die revision R only)  
s AEC-Q100  
s PPAP submission  
5. -062E is only available for die Rev. E and die Rev. R.  
CCMTD-1406124318-10419  
8gb_auto_ddr4_dram.pdf - Rev. L 12/2023 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
1
¥ 2016 Micron Technology, Inc. All rights reserved.  
Products and specifications discussed herein are subject to change by Micron without notice.  

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