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MT40A1G4HX-093E PDF预览

MT40A1G4HX-093E

更新时间: 2024-11-19 00:54:59
品牌 Logo 应用领域
镁光 - MICRON 动态存储器双倍数据速率
页数 文件大小 规格书
365页 11193K
描述
4Gb: x4, x8, x16 DDR4 SDRAM

MT40A1G4HX-093E 数据手册

 浏览型号MT40A1G4HX-093E的Datasheet PDF文件第2页浏览型号MT40A1G4HX-093E的Datasheet PDF文件第3页浏览型号MT40A1G4HX-093E的Datasheet PDF文件第4页浏览型号MT40A1G4HX-093E的Datasheet PDF文件第5页浏览型号MT40A1G4HX-093E的Datasheet PDF文件第6页浏览型号MT40A1G4HX-093E的Datasheet PDF文件第7页 
4Gb: x4, x8, x16 DDR4 SDRAM  
Features  
DDR4 SDRAM  
MT40A1G4  
MT40A512M8  
MT40A256M16  
Options1  
Marking  
Features  
• VDD = VDDQ = 1.2V ±±60V  
• VPP = 2.5V, 1250V/+2560V  
• On-die, internal, adjustable VREFDQ generation  
• 1.2V pseudo open-drain I/O  
• Configuration  
– 1 Gig x 4  
– 512 Meg x 8  
– 25± Meg x 1±  
1G4  
512M8  
25±M1±2  
• FBGA package (Pb-free) – x4, x8  
– 78-ball (900 x 11.500) – Rev. A  
– 78-ball (900 x 16.500) – Rev. B  
• FBGA package (Pb-free) – x1±  
– 9±-ball (900 x 1400) – Rev. A  
– 9±-ball (900 x 1400) – Rev. B  
• Ti0ing – cycle ti0e  
– 6.±25ns @ CL = 22 (DDR4-3266)  
– 6.±82ns @ CL = 26 (DDR4-2933)  
– 6.±82ns @ CL = 21 (DDR4-2933)  
– 6.756ns @ CL = 18 (DDR4-2±±±)  
– 6.756ns @ CL = 19 (DDR4-2±±±)  
– 6.833ns @ CL = 1± (DDR4-2466)  
– 6.833ns @ CL = 17 (DDR4-2466)  
– 6.937ns @ CL = 15 (DDR4-2133)  
– 6.937ns @ CL = 1± (DDR4-2133)  
– 1.671ns @ CL = 13 (DDR4-18±±)  
• Operating te0perature  
• TC 0axi0u0 up to 95°C  
HX  
RH  
– ±40s, 8192-cycle refresh up to 85°C  
– 320s, 8192-cycle refresh at >85°C to 95°C  
• 1± internal banks (x4, x8): 4 groups of 4 banks each  
• 8 internal banks (x1±): 2 groups of 4 banks each  
• 8n-bit prefetch architecture  
• Progra00able data strobe prea0bles  
• Data strobe prea0ble training  
• Co00and/Address latency (CAL)  
• Multipurpose register READ and WRITE capability  
• Write and read leveling  
HA  
GE  
-6±2E  
-6±8E  
-6±8  
-675E  
-675  
-683E  
-683  
-693E  
-693  
• Self refresh 0ode  
• Low-power auto self refresh (LPASR)  
Te0perature controlled refresh (TCR)  
• Fine granularity refresh  
• Self refresh abort  
• Maxi0u0 power saving  
• Output driver calibration  
• No0inal, park, and dyna0ic on-die ter0ination  
(ODT)  
• Data bus inversion (DBI) for data bus  
• Co00and/Address (CA) parity  
• Databus write cyclic redundancy check (CRC)  
• Per-DRAM addressability  
-167E  
– Co00ercial (6° TC 95°C)  
– Industrial (–46° TC 95°C)  
– Revision  
None  
IT  
:A  
:B  
1. Not all options listed can be combined to  
define an offered product. Use the part  
catalog search on http://www.micron.com  
for available offerings.  
Notes:  
• Connectivity test (x1±)  
• sPPR and hPPR capability  
• JEDEC JESD-79-4 co0pliant  
2. Not available on Rev. A.  
3. Restricted and limited availability.  
09005aef84af6dd0  
4gb_ddr4_dram.pdf - Rev. G 1/17 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
1
‹ 2014 Micron Technology, Inc. All rights reserved.  
Products and specifications discussed herein are subject to change by Micron without notice.  

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