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MT40A1G16RC-062E IT PDF预览

MT40A1G16RC-062E IT

更新时间: 2024-11-19 17:00:23
品牌 Logo 应用领域
镁光 - MICRON 动态存储器双倍数据速率
页数 文件大小 规格书
372页 13728K
描述
16Gb: x4, x8, x16 DDR4 SDRAM, MT40A4G4SA-062E

MT40A1G16RC-062E IT 数据手册

 浏览型号MT40A1G16RC-062E IT的Datasheet PDF文件第2页浏览型号MT40A1G16RC-062E IT的Datasheet PDF文件第3页浏览型号MT40A1G16RC-062E IT的Datasheet PDF文件第4页浏览型号MT40A1G16RC-062E IT的Datasheet PDF文件第5页浏览型号MT40A1G16RC-062E IT的Datasheet PDF文件第6页浏览型号MT40A1G16RC-062E IT的Datasheet PDF文件第7页 
16Gb: x4, x8, x16 DDR4 SDRAM  
Features  
DDR4 SDRAM  
MT40A4G4  
MT40A2G8  
MT40A1G16  
s Connectivity test  
s JEDEC JESD-79-4 compliant  
s sPPR and hPPR capability  
s MBIST-PPR support (Die Revision F only)  
Features  
s VDD = VDDQ = 1.2V ά60mV  
s VPP ꢀ ꢁꢂꢃ6ꢄ nꢅꢁꢃM6ꢄ ꢆꢁꢃꢇM6  
s On-die, internal, adjustable VREFDQ generation  
s 1.2V pseudo open-drain I/O  
Options1  
s Configuration  
n 4 Gig x 4  
n 2 Gig x 8  
Marking  
s TC maximum up to 95ιC  
n 64ms, 8192-cycle refresh up to 85ιC  
n 32ms, 8192-cycle refresh at >85ιC to 95ιC  
s 16 internal banks (x4, x8): 4 groups of 4 banks each  
s 8 internal banks (x16): 2 groups of 4 banks each  
s 8n-bit prefetch architecture  
s Programmable data strobe preambles  
s Data strobe preamble training  
s Command/Address latency (CAL)  
s Multipurpose register READ and WRITE capability  
s Write leveling  
4G4  
2G8  
1G16  
n 1 Gig x 16  
s ꢈꢉꢊBALL &"'! PACKAGE ꢋ0BꢊFREEꢌ n Xꢍꢄ Xꢉ  
n ꢅꢇMM X ꢅꢅMM n 2EVꢂ "  
n ꢎMM X ꢅꢅMM n 2EVꢂ %  
n ꢈꢂꢃMM X ꢅꢅMM n 2EVꢂ &  
s ꢎꢏꢊBALL &"'! PACKAGE ꢋ0BꢊFREEꢌ n Xꢅꢏ  
n ꢅꢇMM X ꢅꢐMM n 2EVꢂ "  
n ꢎMM X ꢅꢐMM n 2EVꢂ %  
n ꢈꢂꢃMM X ꢅꢐMM n 2EVꢂ &  
s 4IMING n CYCLE TIME  
n 0.625ns @ CL = 22 (DDR4-3200)  
n 0.682ns @ CL = 21 (DDR4-2933)  
s Operating temperature  
n Commercial (0ι ζ TC ζ 95ιC)  
n )NDUSTRIAL ꢋnꢍꢇι ζ TC ζ 95ιC)  
s Die Revision  
VA  
JC  
SA  
RC  
KD  
TB  
s Self refresh mode  
s Low-power auto self refresh (LPASR)  
s Temperature controlled refresh (TCR)  
s Fine granularity refresh  
s Self refresh abort  
s Maximum power saving  
s Output driver calibration  
s Nominal, park, and dynamic on-die termination  
(ODT)  
s Data bus inversion (DBI) for data bus  
s Command/Address (CA) parity  
s Databus write cyclic redundancy check (CRC)  
s Per-DRAM addressability  
-062E  
-068  
None  
IT  
:B, :E, :F  
Notes: 1. Not all options listed can be combined to  
define an offered product. Use the part  
catalog search on http://www.micron.com for  
available offerings.  
Table 1: Key Timing Parameters  
Speed Grade1  
-062E  
Data Rate (MT/s)  
Target CL-nRCD-nRP  
22-22-22  
tAA (ns)  
13.75  
tRCD (ns)  
13.75  
tRP (ns)  
13.75  
3200  
2933  
-068  
21-21-21  
14.32 (13.75)  
14.32 (13.75)  
14.32 (13.75)  
Notes: 1. Refer to the Speed Bin Tables for additional details.  
CCM005-1406124318-10453  
16gb_ddr4_dram.pdf - Rev. H 8/2021 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
1
¥ 2018 Micron Technology, Inc. All rights reserved.  
Products and specifications discussed herein are subject to change by Micron without notice.  

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Programmable data strobe preambles