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MT36HTF51272FZ-80E PDF预览

MT36HTF51272FZ-80E

更新时间: 2024-03-03 10:09:29
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镁光 - MICRON /
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14页 350K
描述

MT36HTF51272FZ-80E 数据手册

 浏览型号MT36HTF51272FZ-80E的Datasheet PDF文件第2页浏览型号MT36HTF51272FZ-80E的Datasheet PDF文件第3页浏览型号MT36HTF51272FZ-80E的Datasheet PDF文件第4页浏览型号MT36HTF51272FZ-80E的Datasheet PDF文件第5页浏览型号MT36HTF51272FZ-80E的Datasheet PDF文件第6页浏览型号MT36HTF51272FZ-80E的Datasheet PDF文件第7页 
2GB, 4GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM  
Features  
DDR2 SDRAM FBDIMM  
MT36HTF25672FZ – 2GB  
MT36HTF51272FZ – 4GB  
Figure 1: 240-Pin FBDIMM (MO-256 R/C E)  
Features  
• DDR2 functionality and operations supported as de-  
fined in the component data sheet  
Module height: 30.35mm (1.19in)  
• 240-pin, fully buffered dual in-line memory module  
(FBDIMM)  
• Fast data transfer rates: PC2-6400, PC2-5300, or  
PC2-4200  
Options  
Marking  
• 2GB (256 Meg x 72), 4GB (512 Meg x 72)  
• Package  
• 3.2 Gb/s, 4 Gb/s, or 4.8 Gb/s link transfer rates  
– 240-pin DIMM (halogen-free)  
• Frequency/CAS latency  
– 2.5ns @ CL = 5 (DDR2-800)  
– 3.0ns @ CL = 5 (DDR2-667)  
Z
• High-speed, 1.5V differential, point-to-point link  
between the host controller and advanced memory  
buffer (AMB)  
-80E  
-667  
• Fault-tolerant; can work around a bad bit lane in  
each direction  
Features (Continued)  
• High-density scaling with up to eight FBDIMM  
devices per channel  
• Mixed-signal built-in self-test (MBIST) and inter-  
rupt-driven built-in self-test (IBIST) test functions  
• SMBus interface to AMB for configuration register  
access  
• Transparent mode for DRAM test support  
• VDD = VDDQ = 1.8V for DRAM  
• In-band and out-of-band command access  
• Deterministic protocol  
• VREF = 0.9V SDRAM command and address termina-  
tion  
– Enables memory controller to optimize DRAM  
accesses for maximum performance  
• VCC = 1.5V for AMB  
• VDDSPD = 3–3.6V for AMB and EEPROM  
• Serial presence-detect (SPD) with EEPROM  
• Gold edge contacts  
– Delivers precise control and repeatable memory  
behavior  
• Automatic DDR2 SDRAM bus and channel calibra-  
tion  
• Dual-rank  
• Supports 95°C operation with 2X refresh  
• Transmitter de-emphasis to reduce intersymbol in-  
terference (ISI)  
Table 1: Key Timing Parameters  
Data Rate (MT/s)  
Speed  
Grade Industry Nomenclature  
CL = 6  
CL = 5  
800  
667  
CL = 4  
533  
CL = 3  
400  
tRCD (ns)  
tRP (ns) tRC (ns)  
-80E  
-667  
-53E  
PC2-6400  
PC2-5300  
PC2-4200  
800  
12.5  
15  
12.5  
15  
55  
55  
55  
533  
400  
533  
400  
15  
15  
PDF: 09005aef83d491e1  
htf36c256_512x72fz.pdf - Rev. D 4/14 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
1
© 2009 Micron Technology, Inc. All rights reserved.  
Products and specifications discussed herein are subject to change by Micron without notice.  

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