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MT29GZ5A5BPGGA-53IT PDF预览

MT29GZ5A5BPGGA-53IT

更新时间: 2024-09-15 15:18:47
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镁光 - MICRON /
页数 文件大小 规格书
397页 10983K
描述
MT29GZ5A5BPGGA-53IT.87J, MT29GZ5A5BPGGA-046IT.87J

MT29GZ5A5BPGGA-53IT 数据手册

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Micron Confidential and Proprietary  
149-Ball NAND Flash with LPDDR4/LPDDR4X MCP  
Features  
NAND Flash with Mobile LPDDR4/  
LPDDR4X 149-Ball MCP  
MT29GZ5A5BPGGA-53IT.87J, MT29GZ5A5BPGGA-046IT.87J  
Figure 1: MCP Block Diagram  
Features  
• Micron® NAND Flash and LPDDR4/LPDDR4X compo-  
nents  
• RoHS-compliant, “green” package  
• Separate NAND Flash and LPDDR4/LPDDR4X interfa-  
ces  
NAND Flash  
Device  
NAND Flash  
Interface  
NAND Flash  
Power  
• Space-saving multichip package (MCP)  
• Low-voltage operation  
• Industrial temperature range: –40°C to +85°C  
LPDRAM  
Device  
LPDRAM  
Interface  
NAND Flash-Specific Features  
• Organization  
LPDRAM Power  
– Page size x8: 4352 bytes (4096 + 256 bytes)  
– Block size: 64 pages  
– Number of planes: 1  
• VCC = 1.70–1.95V; 1.80V nominal  
Mobile LPDDR4/LPDDR4X-Specific Fea-  
tures (Continued)  
• Programmable READ and WRITE latencies (RL/WL)  
• Programmable and on-the-fly burst lengths (BL =  
16, 32)  
• Directed per-bank refresh for concurrent bank op-  
eration and ease of command scheduling  
• On-chip temperature sensor to control self refresh  
rate  
• Partial-array self refresh (PASR)  
• Selectable output drive strength (DS)  
• Programmable VSS (ODT) termination  
Mobile LPDDR4/LPDDR4X-Specific Fea-  
tures  
• Ultra-low-voltage core and I/O power supply  
– VDD1 = 1.70–1.95V; 1.80V nominal  
– VDD2 = 1.06–1.17V; 1.1V nominal  
– VDDQ = 1.06–1.17V; 1.10V nominal  
or Low VDDQ = 0.57–0.65V; 0.60V nominal  
• Frequency range  
– 2133–10 MHz (data rate range: 4266–20 Mb/s/  
pin)  
• 16n prefetch DDR architecture  
• 8 internal banks per channel for concurrent opera-  
tion  
1. For physical part markings, see Part Num-  
bering Information.  
Note:  
• Single-data-rate CMD/ADR entry  
• Bidirectional/differential data strobe per byte lane  
Table 1: Key Timing Parameters  
WRITE Latency  
READ Latency  
Speed  
Grade  
Clock Rate  
(MHz)  
Data Rate  
(Mb/s/pin)  
Set A  
Set B  
30  
DBI Disabled  
DBI Enabled  
-53  
1866  
2133  
3733  
4266  
16  
18  
32  
36  
36  
40  
-046  
34  
CCM005-284460984-10460  
149ball_nand_lpddr4_lpddr4x_j87j.pdf – Rev. F 3/2020 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
© 2017 Micron Technology, Inc. All rights reserved.  
1
Products and specifications discussed herein are subject to change by Micron without notice.  

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