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MT16LSDF6464LHY-13E PDF预览

MT16LSDF6464LHY-13E

更新时间: 2024-11-07 00:51:51
品牌 Logo 应用领域
镁光 - MICRON 时钟动态存储器光电二极管内存集成电路
页数 文件大小 规格书
22页 476K
描述
SMALL-OUTLINE SDRAM MODULE

MT16LSDF6464LHY-13E 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:DIMM, DIMM144,32Reach Compliance Code:compliant
风险等级:5.75最长访问时间:5.4 ns
最大时钟频率 (fCLK):143 MHzI/O 类型:COMMON
JESD-30 代码:R-PDMA-N144内存密度:4294967296 bit
内存集成电路类型:SYNCHRONOUS DRAM MODULE内存宽度:64
端子数量:144字数:67108864 words
字数代码:64000000最高工作温度:70 °C
最低工作温度:组织:64MX64
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:DIMM封装等效代码:DIMM144,32
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
电源:3.3 V认证状态:Not Qualified
刷新周期:8192最大待机电流:0.032 A
子类别:DRAMs最大压摆率:4.56 mA
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子节距:0.8 mm
端子位置:DUALBase Number Matches:1

MT16LSDF6464LHY-13E 数据手册

 浏览型号MT16LSDF6464LHY-13E的Datasheet PDF文件第2页浏览型号MT16LSDF6464LHY-13E的Datasheet PDF文件第3页浏览型号MT16LSDF6464LHY-13E的Datasheet PDF文件第4页浏览型号MT16LSDF6464LHY-13E的Datasheet PDF文件第5页浏览型号MT16LSDF6464LHY-13E的Datasheet PDF文件第6页浏览型号MT16LSDF6464LHY-13E的Datasheet PDF文件第7页 
256MB, 512MB (x64, DR)  
144-PIN SDRAM SODIMM  
MT16LSDF3264(L)H – 256MB  
MT16LSDF6464(L)H – 512MB  
For the latest data sheet, please refer to the Micron® Web  
site: www.micron.com/products/modules  
SMALL-OUTLINE  
SDRAM MODULE  
Features  
Figure 1: 144-Pin SODIMM (MO-190)  
PC100- and PC133-compliant, 144-pin, small-  
outline, dual in-line memory module (SODIMM)  
Utilizes 100 MHz and 133 MHz SDRAM components  
Unbuffered  
PCB height: 1.25in (31.75mm)  
256MB (32 Meg x 64) and 512MB (64 Meg x 64)  
Single +3.3V power supply  
Fully synchronous; all signals registered on positive  
edge of system clock  
Internal pipelined operation; column address can  
be changed every clock cycle  
Internal SDRAM banks for hiding row access/  
precharge  
Programmable burst lengths: 1, 2, 4, 8, or full page  
Auto precharge and auto refresh modes  
Self refresh mode: standard and low-power  
256MB module: 64ms, 4,096-cycle refresh (15.625µs  
refresh interval); 512MB: 64ms, 8,192-cycle refresh  
(7.81µs refresh interval)  
LVTTL-compatible inputs and outputs  
Serial presence-detect (SPD)  
Gold edge connectors  
Options  
Marking  
Self refresh current  
Standard  
Low power  
Package  
144-pin SODIMM (standard)  
144-pin SODIMM (lead-free)  
Memory Clock/CL  
7.5ns (133 MHz)/CL = 2  
7.5ns (133 MHz)/CL = 3  
10ns (100 MHz)/CL = 2  
PCB  
None  
1
L
G
1
Y
Table 1:  
CL = CAS (READ) latency  
Timing Parameters  
-13E  
-133  
-10E  
ACCESS TIME  
MARKING FREQUENCY CL = 2 CL = 3 TIME TIME  
MODULE  
CLOCK  
SETUP HOLD  
Height 1.25in (31.75mm)  
See page 2 note  
-13E  
-133  
-10E  
133 MHz  
133 MHz  
100 MHz  
5.4ns  
5.4ns  
1.5ns 0.8ns  
1.5ns 0.8ns  
NOTE: 1. Contact Micron for product availability.  
6ns  
2ns  
1ns  
Table 2:  
Address Table  
256MB  
512MB  
4K  
8K  
Refresh count  
Device banks  
Device configuration  
Row addressing  
Column addressing  
Module ranks  
4 (BA0, BA1)  
128Mb (16 Meg x 8)  
4K (A0–A11)  
1K (A0–A9)  
4 (BA0, BA1)  
256Mb (32 Meg x 8)  
8K (A0–A12)  
1K (A0–A9)  
2 (S0#, S1#)  
2 (S0#, S1#))  
pdf: 09005aef807924d2, source: 09005aef807924f1  
SDF16C32_64x64HG.fm - Rev. E 4/06 EN  
1
©2006 Micron Technology, Inc. All rights reserved.  
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.  

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